Accelerator Output Buffers Using Partial Address Memory Requests
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Solution Overview
Problem
Conventional computing architectures experience increased data transfer latency and computational delays due to serialized data communication between accelerators and a centralized output structure, particularly in systems with multiple accelerators producing data at different rates.
Innovation Solution
Implementing a processing-in-memory component that processes data locally and generates output independently of traffic on the connection to the host, using partial address memory requests to notify the host when data is ready for consumption, thereby avoiding the need for serialized data communication and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If accelerators write data to a centralized output structure (memory) before the host reads it, then data can be stored and accessed by the host, but data transfer latency increases and computational pipeline is blocked
Solution Approach 1:
The patent extracts the output data from the centralized memory and places it directly into output buffers within the accelerator itself. This allows the host to read data directly from the accelerator's local buffers without waiting for data to be written to and read from centralized memory, thereby reducing data transfer latency while maintaining data availability.
Solution Approach 2:
The patent introduces output buffers as an intermediary structure between the accelerator and the host. These buffers serve as a local staging area that decouples the data production rate of the accelerator from the data consumption rate of the host, enabling continuous computation without blocking the computational pipeline due to memory write operations.
2Reliability
If the host waits for accelerators to complete computations and write data to memory before reading, then data integrity is maintained, but computational pipeline efficiency decreases
Solution Approach 1:
The patent implements preliminary action by having accelerators proactively write computation results directly to their local output buffers as soon as the computations are complete, rather than waiting for the host to initiate a read operation. This allows the host to simply read from the buffers at its own pace, maintaining data integrity while preventing the computational pipeline from stalling.
Solution Approach 2:
The patent enables continuity of useful action by allowing the computational pipeline to proceed without interruption. Accelerators can continuously perform computations and stage results in local buffers, while the host independently reads from these buffers at its own rate, ensuring that computation operations are not blocked by memory write latency.
3Adaptability or versatility
If multiple accelerators communicate through a single centralized output structure, then data can be aggregated, but communication bandwidth becomes a bottleneck
Solution Approach 1:
The patent applies segmentation by dividing the centralized output structure into multiple distributed output buffers, with each accelerator having its own dedicated buffer. This eliminates the communication bottleneck by allowing multiple accelerators to write to their respective buffers in parallel, while the host can read from multiple buffers simultaneously, thereby maintaining data aggregation capability while increasing communication bandwidth.
Data Source
AI summary
Partial address memory requests for data are described. In accordance with the described techniques, an accelerator receives a request for data that does not include address information for a data storage location from which the data is to be retrieved. The accelerator identifies at least one data storage location that includes data produced by the accelerator and retrieves the data from the at least one data storage location. A result is then output by the accelerator that includes the data retrieved from the at least one data storage location.