Hierarchical Accelerator Registry for NFV Performance Predictability
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Solution Overview
Problem
Network Functions Virtualization (NFV) faces challenges in performance predictability due to resource contention and overhead in hosted virtualization implementations, which can lead to increased latency and variability, especially in high-performance applications.
Innovation Solution
A NFV platform is introduced that includes a host processor coupled with a reconfigurable coprocessor serving as a hardware accelerator, featuring a virtualization accelerator management module that maintains a hierarchical accelerator resource availability registry. This registry categorizes resources by latency, allowing for optimized resource allocation and dynamic reconfigurability to enhance performance predictability and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If hosted virtualization techniques are used to run network functions on commodity hardware, then capital expenditure and operating expenditure are reduced, but performance predictability and latency are worsened due to resource contention and overhead
Solution Approach 1:
The patent segments the virtualization architecture into multiple layers: hosted virtualization layer for cost-effective commodity hardware utilization, and a hardware acceleration layer with dedicated coprocessors for performance-critical network functions. This segmentation allows each layer to handle specific tasks optimally, resolving the contradiction between cost reduction and performance predictability.
Solution Approach 2:
The patent introduces hardware accelerators (coprocessors) as intermediary components between the hosted virtualization environment and the physical network functions. These accelerators mediate the resource contention issues by providing dedicated hardware resources that can be dynamically allocated to virtual machines, thereby maintaining performance predictability while utilizing commodity hardware through virtualization.
2Loss of time
If hardware accelerators are introduced to improve performance predictability, then latency is reduced, but device complexity increases
Solution Approach 1:
The patent designs universal hardware accelerators (coprocessors) that can perform multiple network functions through reconfiguration. Instead of requiring separate dedicated hardware for each network function (which would increase complexity), a single multi-functional accelerator can be dynamically reconfigured to handle different functions such as firewalling, NAT, intrusion detection, and load balancing, thereby reducing overall device complexity while maintaining low latency.
Solution Approach 2:
The patent implements dynamic reconfiguration capabilities in the hardware accelerators, allowing them to adapt their functionality based on real-time network requirements. This dynamic nature enables the system to optimize performance for specific functions when needed while maintaining a simplified hardware architecture, resolving the contradiction between latency reduction and device complexity.
3Reliability
If custom application-specific integrated circuits are used to build networks, then performance and reliability are improved, but adaptability and ease of making changes are worsened
Solution Approach 1:
The patent replaces static custom ASICs with dynamic reconfigurable hardware accelerators. These accelerators can be programmatically reconfigured to implement different network functions and protocols, providing the adaptability of software while maintaining the performance and reliability of hardware. This resolves the contradiction by enabling both high reliability and ease of modification through a unified reconfigurable platform.
Solution Approach 2:
The patent uses virtualization to create virtual copies of network functions that can be replicated and distributed across multiple physical hosts. Instead of modifying physical custom hardware, the system creates virtual instances that can be easily copied, moved, and managed software-defined, thereby maintaining hardware reliability while achieving software-level adaptability.
Data Source
AI summary
A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. To help improve performance predictability, a hierarchical accelerator registry may be maintained on the coprocessor and/or on local servers. The accelerator registry may assign different classes and speed grades to various types of available resources to help the virtualized network better predict certain task latencies. The accelerator registry may be periodically updated based on changes detected in the local storage and hardware or based on changes detected in remote networks.