Hardware Accelerator Repeat Control for Pipeline Latency Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Radar systems face significant performance impairments due to large initial pipeline latencies when executing accelerator instructions multiple times, particularly with short vector lengths, leading to increased execution cycles and latency penalties.
Innovation Solution
A repeat instruction is introduced that specifies a repetition count and automatically updates start and destination addresses for each execution of a subsequent accelerator instruction, reducing pipeline latency by configuring the command sequencer to execute the instruction multiple times with a single initial setup, thereby minimizing latency penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If accelerator instructions are executed multiple times with separate initial pipeline setups, then each execution can be completed independently, but the total execution cycles increase significantly due to repeated pipeline latency penalties
Solution Approach 1:
The patent merges multiple separate accelerator instruction executions into a single unified execution flow by introducing a repeat counter mechanism. The command sequencer combines the initialization phase (pipeline setup) with subsequent repeated executions, so that the pipeline latency penalty is paid only once rather than repeatedly for each execution. This is achieved by configuring the repeat counter to control the number of repetitions and automatically managing the execution loop within the hardware accelerator.
2Adaptability or versatility
If the same accelerator instruction is run multiple times with different addresses, then processing flexibility is maintained, but the initial pipeline penalty is repeatedly incurred
Solution Approach 1:
The patent introduces dynamic address generation within the repeat execution mechanism. The address input generator dynamically updates source and destination addresses for each repetition of the accelerator instruction, allowing the same instruction to operate on different data regions without requiring separate instruction fetches. This dynamic address management enables the system to maintain adaptability while avoiding repeated pipeline latency penalties, as the instruction body is executed repeatedly with automatically updated addresses controlled by the repeat counter.
Data Source
AI summary
A method and circuit for a data processing system provide a hardware accelerator repeat control instruction (402A) which is executed with a hardware accelerator instruction (402B) to extract and latch repeat parameters from the hardware accelerator repeat control instruction, such as a repeat count value (RPT_CNT), a source address offset value (ADDR_INCR0), and a destination address offset value (ADDR_INCR1), and to generate a command to the hardware accelerator (205) to execute the hardware accelerator instruction a specified plurality of times based on instruction parameters from the hardware accelerator instruction by using the repeat count value to track how many times the hardware accelerator instruction is executed and by automatically generating, at each execution of the hardware accelerator instruction, additional source and destination addresses for the hardware accelerator from the repeat parameters until the hardware accelerator instruction has been executed the specified plurality of times by the hardware accelerator.