Configurable Accelerator Scheduler for Latency and Throughput Tradeoffs
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Solution Overview
Problem
Designing ASIC cores with hardware accelerators is challenging due to conflicting design tradeoff priorities between physical size, performance, latency, and throughput, making it difficult to achieve broad usage across various applications.
Innovation Solution
A reusable hardware control structure for a hardware acceleration engine that can be configured to optimize design characteristics such as latency and blocking patterns, allowing for flexible selection of configuration options to meet specific application requirements, implemented through a scheduler control structure within an integrated circuit core.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware accelerators are designed with fixed configuration for specific functions, then performance and throughput are optimized for that specific application, but adaptability to other applications is reduced
Solution Approach 1:
The patent implements a configurable hardware accelerator with dynamic control structures that allow the same hardware to be reconfigured for different applications. The scheduler control structure can be programmed with different configuration parameters (N, M, K values) to optimize performance for various computational tasks, transforming a static design into a dynamic, adaptable system.
Solution Approach 2:
The invention changes structural parameters of the hardware accelerator (buffer sizes, pipeline stages, parallelism factors) to optimize performance for different applications. By allowing configuration of parameters such as the number of parallel processing units and buffer depths, the system can adapt its characteristics to match specific application requirements while maintaining the same physical hardware.
2Adaptability or versatility
If hardware accelerator configuration is made configurable for different applications, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent creates a universal hardware accelerator architecture that can perform multiple functions through configuration rather than requiring separate dedicated hardware for each function. The same physical structure serves different computational tasks by changing control parameters, reducing overall system complexity compared to having multiple specialized accelerators.
Solution Approach 2:
The configurable accelerator is divided into modular functional blocks (processing units, buffers, control logic) that can be independently configured. This segmentation allows complex functionality to be achieved through simple configuration of individual modules rather than requiring complex custom design for each application.
3Adaptability or versatility
If more configuration options are provided in hardware accelerators, then versatility across applications is improved, but ease of manufacture and design simplification is reduced
Solution Approach 1:
The patent pre-configures the hardware accelerator with a set of standardized configuration options and control structures during manufacturing. These preliminary configurations cover common application scenarios, allowing the hardware to be manufactured once with built-in flexibility rather than requiring custom design and manufacturing for each application.
Data Source
AI summary
A reusable hardware control structure is provided for a hardware acceleration engine that can be configured for implementation within an electronic integrated circuit design according to any one of a plurality of configuration alternatives. The reusable hardware control structure comprises a digital logic circuit design developed to receive configuration data from the hardware acceleration engine describing a selected configuration alternative. The selected configuration alternative is any one of the plurality of configuration alternatives. The digital logic circuit design is developed to process the configuration data to provide an evaluation of an input-to-output latency and an input blocking pattern of the hardware acceleration engine configured according to the selected configuration alternative. The evaluation is capable of being leveraged by control logic within the electronic integrated circuit design to increase utilization of the hardware acceleration engine.