Accelerator Sharing via Multiple Coherent Proxies

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Solution Overview

Problem

Current off-chip coherent accelerator solutions suffer from long access latency, reduced SMP bandwidth efficiency, and poor coherent proxy hardware utilization due to the limitation of sharing accelerators with only one coherent proxy across multiple processors.

Innovation Solution

Implementing a system where an accelerator is shared among multiple processors through multiple coherent proxies, with each proxy maintaining a shadow directory for cache lines allocated to it, allowing for efficient communication and cache coherency management across the processors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If an accelerator is shared among multiple processors through a single coherent proxy, then device complexity is reduced, but access latency increases and bandwidth efficiency decreases

Engineering Contradiction:
Improvecoherent proxy hardware utilizationVSAvoidaccess latency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent segments the single coherent proxy into multiple coherent proxies (first coherent proxy and second coherent proxy), each capable of independently handling requests from different processors. This segmentation allows parallel request processing, reducing access latency while maintaining manageable device complexity through modular architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension to the proxy architecture by adding multiple coherent proxies operating in parallel rather than a single sequential proxy. This dimensional expansion from 1D (single proxy) to 2D (multiple proxies) enables concurrent request handling and improves bandwidth efficiency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If an accelerator is shared among multiple processors through a single coherent proxy, then device complexity is reduced, but bandwidth efficiency is reduced

Engineering Contradiction:
Improvecoherent proxy hardware utilizationVSAvoidbandwidth efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the single coherent proxy into multiple coherent proxies, each capable of independently handling requests from different processors. This segmentation allows parallel request processing, improving bandwidth efficiency while maintaining manageable device complexity through modular architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent enables continuous useful action by allowing multiple coherent proxies to operate simultaneously and independently, eliminating idle time and ensuring that the accelerator resource is continuously utilized. Each proxy can process requests without waiting for others, maximizing bandwidth efficiency.

Inventive Principle:
Principle #20Continuity of useful action

3Loss of time

If cache lines are allocated to multiple coherent proxies, then access latency is reduced, but device complexity increases

Engineering Contradiction:
Improveaccess latencyVSAvoidcache coherency management
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent uses copying by creating shadow directories in each coherent proxy that mirror the main cache directory. Each coherent proxy maintains a local copy (shadow directory) of the cache line allocation information, allowing independent and fast access to coherency data without centralized bottlenecks, thus reducing access latency while managing complexity through replicated information.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent applies local quality by giving each coherent proxy its own shadow directory tailored to its specific needs. Each proxy maintains local coherency information relevant to its assigned processors, enabling localized decision-making and reducing the need for complex global coordination, thus balancing access speed with manageable complexity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11068397B2Accelerator sharing
Publication Date: 2021.07.20 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11068397B2 patent drawing
  • US11068397B2 patent drawing
  • US11068397B2 patent drawing

AI summary

Disclosed aspects relate to accelerator sharing among a plurality of processors through a plurality of coherent proxies. The cache lines in a cache associated with the accelerator are allocated to one of the plurality of coherent proxies. In a cache directory for the cache lines used by the accelerator, the status of the cache lines and the identification information of the coherent proxies to which the cache lines are allocated are provided. Each coherent proxy maintains a shadow directory of the cache directory for the cache lines allocated to it. In response to receiving an operation request, a coherent proxy corresponding to the request is determined. The accelerator communicates with the determined coherent proxy for the request.