Hardware Accelerator Conditional Flow Control
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Solution Overview
Problem
Cameras and other devices with limited processing power face challenges in performing image processing tasks like computer vision due to the need for explicit data transfer between heterogeneous processors, which increases code complexity, reduces portability, and consumes time and power.
Innovation Solution
A system and method that utilize a hardware accelerator to perform splitter and combiner operations, allowing data to be processed and flagged as active or inactive based on decision values, thereby minimizing data movement and enabling efficient handling of divergent control flow, even with limited processing power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If explicit data transfer is performed between heterogeneous processors, then code complexity increases and portability decreases, but data processing can be performed on specialized hardware
Solution Approach 1:
The patent introduces an intermediary data structure (active/inactive flags) that mediates between the general-purpose processor and hardware accelerator. This intermediary mechanism allows conditional flow control to be handled within the hardware accelerator without requiring explicit data transfers back to the general-purpose processor, thereby reducing code complexity while maintaining specialized hardware processing capabilities.
Solution Approach 2:
The patent segments the data flow into multiple independent branches, each with its own active/inactive flag status. This segmentation allows different data paths to be processed independently in parallel on the hardware accelerator, improving productivity while the flag-based control mechanism keeps the overall system manageable and portable.
2Productivity
If explicit data transfer is performed between heterogeneous processors, then code portability decreases, but hardware acceleration can be utilized
Solution Approach 1:
The patent implements a universal flag-based control mechanism that can work with different hardware accelerator architectures and programming models. The active/inactive flag system provides a portable interface that abstracts the underlying hardware differences, allowing the same code to run on various heterogeneous processor configurations while still utilizing hardware acceleration for improved processing speed.
3Productivity
If data is transferred between heterogeneous processors, then power consumption increases, but complex image processing tasks can be performed
Solution Approach 1:
The patent extracts the conditional flow control logic from the general-purpose processor and implements it directly in the hardware accelerator using active/inactive flags. This extraction eliminates the need for repeated data transfers between processors, reducing power consumption while maintaining the capability to perform complex image processing tasks on the hardware accelerator.
4Ease of operation
If conditional flow is handled by transferring data between processors, then processing time increases, but control flow can be managed
Solution Approach 1:
The patent uses active/inactive flags as an intermediary control mechanism that enables conditional flow management entirely within the hardware accelerator. This intermediary approach allows control flow decisions to be made and executed in parallel without requiring sequential data transfers between processors, thereby maintaining ease of control flow management while significantly reducing processing time.
Data Source
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AI summary
A method and system are disclosed. The method may include receiving instructions in a hardware accelerator coupled to a computing device. The instructions may describe operations and data dependencies between the operations. The operations and the data dependencies may be predetermined. The method may include performing a splitter operation in the hardware accelerator, performing an operation in each of a plurality of branches, and performing a combiner operation in the hardware accelerator.