General-Purpose Computing Accelerator with State-Controlled Instruction Routing
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Solution Overview
Problem
Conventional supercomputer systems face limitations in scalability and versatility due to the combination of central processing units (CPUs) and graphics processing units (GPUs), which restrict their ability to handle large-scale and diverse computational tasks efficiently.
Innovation Solution
A general-purpose computing accelerator is introduced, featuring a memory with an instruction cache, multiple executing units for different operations, an instruction fetching unit, a decoding unit, and a state control unit that manages instruction flow based on operation states, enabling efficient execution of both general-purpose and matrix operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a super computer is implemented by a combination of CPU and GPU, then computing capability is secured, but scalability and versatility are limited
Solution Approach 1:
The computing accelerator is designed to perform multiple functions by integrating both general-purpose computing capabilities (through the first executing unit that handles arithmetic logic and floating point operations) and matrix operation capabilities (through the second executing unit). This multi-functional design allows a single device to replace the need for separate CPU and GPU systems, improving versatility while maintaining a unified simplified structure.
2Productivity
If the scale of super computer is expanded to exa-scale unit, then computing power is increased, but scalability is limited
Solution Approach 1:
The computing accelerator is divided into distinct functional segments: the first executing unit for general-purpose operations and the second executing unit for matrix operations. This segmentation allows each unit to be independently optimized and scaled. The modular architecture enables the system to be expanded to exa-scale by replicating and interconnecting multiple accelerator units, thereby improving scalability while maintaining high computing power.
3Adaptability or versatility
If multiple executing units are integrated in a single accelerator, then versatility is improved, but device complexity increases
Solution Approach 1:
The state control unit acts as an intermediary that manages the interaction between the first executing unit, the second executing unit, and the memory. It controls the path of instructions based on the operation state of the second executing unit, determining whether instructions are provided to the second executing unit or stored as register files. This intermediary control mechanism simplifies the overall system architecture by providing centralized coordination, thereby improving versatility while preventing internal structure complexity from becoming unmanageable.
Data Source
AI summary
Disclosed is a general-purpose computing accelerator which includes a memory including an instruction cache, a first executing unit performing a first computation operation, a second executing unit performing a second computation operation, an instruction fetching unit fetching an instruction stored in the instruction cache, a decoding unit that decodes the instruction, and a state control unit controlling a path of the instruction depending on an operation state of the second executing unit. The decoding unit provides the instruction to the first executing unit when the instruction is of a first type and provides the instruction to the state control unit when the instruction is of a second type. Depending on the operation state of the second executing unit, the state control unit provides the instruction of the second type to the second executing unit or stores the instruction of the second type as a register file in the memory.