Accelerator Storage Interface Address Notification
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Solution Overview
Problem
The existing information processing apparatuses face bottlenecks in data transfer due to high processing loads on the processor and bus bandwidth, limiting the utilization of rapid storage devices, and there is a lack of description on how the GPU identifies a non-volatile memory array during initialization, preventing the accelerator from accessing the storage device for data read and processing.
Innovation Solution
An information processing apparatus is configured with a processor, memory, and at least one accelerator, where the storage device includes an initial setting interface for initialization instructions and an I/O interface for issuing commands, allowing the processor to notify the accelerator of the storage device's address, enabling the accelerator to identify and access the storage device for data read and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor transfers data from the storage device to system memory and then to the accelerator, then the accelerator can process data, but the bus bandwidth becomes a bottleneck limiting performance improvement
Solution Approach 1:
The patent introduces a memory device as an intermediary component between the storage device and the accelerator. The memory device receives data directly from the storage device and makes it available to the accelerator, eliminating the need for data to traverse the processor and system memory. This intermediary structure resolves the bus bandwidth bottleneck by creating a more direct data path.
2Productivity
If the accelerator and storage device directly communicate without processor intervention, then data transfer efficiency improves, but the accelerator cannot identify the storage device address during initialization
Solution Approach 1:
The memory device serves as an intermediary that facilitates address communication between the accelerator and storage device. During initialization, the memory device receives the storage device address from the processor and makes it available to the accelerator, enabling direct communication while resolving the address identification problem.
Solution Approach 2:
The system performs preliminary address setup during the initialization phase before direct accelerator-storage device communication begins. The processor notifies the memory device of the storage device address during initialization, so that when direct communication starts, the accelerator can immediately access the storage device without further processor intervention.
3Quantity of substance
If the processor handles all data transfer operations, then data can be transferred, but high processing loads on the processor create bottlenecks
Solution Approach 1:
The patent extracts the data transfer function from the processor and relocates it to the memory device. The memory device independently handles data reception from the storage device and makes it available to the accelerator without processor involvement, thereby reducing the processor's processing load and eliminating it as a bottleneck in the data transfer chain.
Data Source
AI summary
An information processing device having a processor and memory, and including one or more accelerators and one or more storage devices, wherein: the information processing device has one network for connecting the processor, the accelerators, and the storage devices; the storage devices have an initialization interface for accepting an initialization instruction from the processor, and an I/O issuance interface for issuing an I/O command; and the processor notifies the accelerators of the address of the initialization interface or the address of the I/O issuance interface.