Automated Hardware Accelerator Test Harness Generation

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Solution Overview

Problem

Conventional hardware accelerator design tools are inefficient, requiring significant manual effort and resources, and are not scalable for asynchronous offloading and function acceleration, especially in systems with multiple processors, leading to performance bottlenecks and increased bandwidth requirements.

Innovation Solution

A system and method for generating hardware accelerators and processor offloads using a parameter queue, result queue, and logic block, enabling asynchronous offloading and point-to-point connections between processors and accelerators, along with automated test harness creation and code generation for efficient function invocation and validation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional hardware accelerator design tools are used, then manual effort and resources are required, but design efficiency and scalability deteriorate

Engineering Contradiction:

Improvedesign effortVSAvoiddesign efficiency

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The system automatically generates hardware accelerator designs, test harnesses, and validation code without requiring manual intervention. The automated design generation engine transforms software functionality descriptions into complete hardware accelerator specifications, eliminating the need for manual design efforts while significantly improving design efficiency and scalability

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The patent replaces manual mechanical design processes with an automated software-based design generation system. Instead of engineers manually creating hardware accelerator designs, the system uses automated tools to generate complete hardware specifications, test harnesses, and validation code from software functionality descriptions

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If synchronous processing is used, then processor waits for accelerator completion, but system throughput deteriorates

Engineering Contradiction:

Improveprocessing correctnessVSAvoidsystem throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The system dynamically switches between synchronous and asynchronous processing modes based on the specific accelerator and task requirements. The framework provides configurable processing modes that allow the system to optimize for either correctness (synchronous) or throughput (asynchronous) depending on the operational context

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent introduces an intermediary layer (the automated design generation framework) that manages the interaction between processor and accelerator. This intermediary handles task scheduling, data transfer coordination, and result collection, enabling efficient asynchronous operation while maintaining processing correctness through automated validation

Inventive Principle:

Principle #24Intermediary (Mediator)

3Device complexity

If multiple processors share common bandwidth, then system complexity is reduced, but bandwidth requirements and performance bottlenecks increase

Engineering Contradiction:

Improvesystem complexityVSAvoidbandwidth requirements

Core Design Contradiction:

Device complexityVSQuantity of substance

Solution Approach 1:

The system segments the bandwidth allocation by creating dedicated point-to-point connections for each processor-accelerator pair. This segmentation eliminates the need for shared bandwidth arbitration and reduces overall bandwidth requirements by allowing parallel data transfers without contention

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a shared bus architecture (one-dimensional bandwidth sharing) to a mesh-like point-to-point connection topology (multi-dimensional parallel pathways). This dimensional change allows multiple processors to access accelerators simultaneously through different connection paths, reducing bandwidth bottlenecks

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

4Loss of time

If automated design generation is implemented, then design time is reduced, but validation and testing complexity increases

Engineering Contradiction:

Improvedesign timeVSAvoidvalidation complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The system merges the design generation and validation creation processes into a single automated workflow. The same design generation engine that creates hardware accelerator specifications also automatically generates corresponding test harnesses and validation code, ensuring consistency between design and validation while reducing overall complexity

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9690630B2Hardware accelerator test harness generation

Publication Date: 2017.06.27 MIPS HLDG INC

AI summary

System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.