Neural Network Accelerator Type Conversion for Multi-Precision AI
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current AI semiconductor technologies face limitations in computational power and efficiency, particularly in handling the increased computation demands of deep learning, leading to high power consumption and physical scaling issues, making it difficult to commercialize AI applications.
Innovation Solution
A neural network accelerator with a polymorphic operator array and type conversion capabilities that supports multi-precision operations, allowing for efficient matrix convolution operations by analyzing instructions, converting data types, and performing operations across different precision layers, thereby optimizing computational and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU and GPU-based architectures are used to improve AI computing performance, then computational power increases, but power consumption increases to several kilowatts making commercialization difficult
Solution Approach 1:
The patent segments the computational tasks by implementing a multi-precision architecture where different precision levels (e.g., low precision for some layers, high precision for others) are applied to different parts of the neural network computation. This allows the system to achieve required AI performance while reducing overall power consumption by avoiding uniform high-precision computation across all layers.
Solution Approach 2:
The patent changes the precision parameter dynamically across different neural network layers. By adjusting the precision level according to the specific requirements of each layer, the system optimizes the balance between computational performance and power consumption, enabling commercialization of AI applications with reduced energy usage.
2Measurement precision
If high precision computation is used throughout the neural network, then computational accuracy is improved, but computational efficiency and power efficiency deteriorate
Solution Approach 1:
The patent applies local quality by assigning different precision levels to different layers of the neural network based on their specific computational requirements. Critical layers that require high accuracy use high precision computation, while less critical layers use lower precision, thereby improving overall computational efficiency without significantly compromising the final output accuracy.
Solution Approach 2:
The patent dynamically changes the precision parameter across different layers and operations within the neural network. This selective precision adjustment allows the system to maintain high computational accuracy where needed while improving overall computational efficiency by reducing precision in appropriate contexts.
3Productivity
If multi-precision operations are supported, then computational efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal polymorphic operator array that can perform multiple precision operations (low precision, high precision, and mixed precision) using a single hardware structure. This multi-functional design achieves computational efficiency across different precision requirements without proportionally increasing device complexity, as the same operator array adapts to different precision modes rather than requiring separate dedicated units for each precision level.
Data Source
AI summary
Disclosed are a neural network accelerator and an operating method thereof, which include an instruction analyzer that analyzes a first instruction instructing an operation with respect to a first layer of a neural network algorithm from an external device, a polymorphic operator array including a plurality of operators that performs the operation with respect to the first layer under a control of the instruction analyzer, an interface that communicates with the external device and an external memory under the control of the instruction analyzer, an internal memory, a type converter, a type conversion data mover that stores data received from the external memory through the interface in the internal memory under the control of the instruction analyzer, and an internal type converter that performs a conversion of data stored in the internal memory or data generated by the polymorphic operator array under the control of the instruction analyzer.