Access-Aware Memory Defragmentation for Tile-Level Power Savings
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Solution Overview
Problem
The increase in power consumption due to leakage current in semiconductor memory systems is a result of semiconductor process miniaturization, necessitating a solution to suppress power consumption.
Innovation Solution
A memory system with tiles that can transition between different power consumption states, combined with a defragmenting device that rearranges data to group high and low access frequency data separately, allowing more tiles to enter low power consumption states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data is uniformly distributed across all tiles, then access speed is maintained, but power consumption increases due to inability to transition tiles to low power states
Solution Approach 1:
The memory is divided into multiple independent tiles, each capable of autonomous power state transitions. This segmentation allows selective power management where only actively used tiles remain in high-power states while others transition to low-power states, resolving the contradiction between power consumption and access speed.
Solution Approach 2:
Different tiles are assigned different power states based on their local data access patterns. Tiles containing frequently accessed data maintain high-power states for fast access, while tiles with infrequently accessed data transition to low-power states, achieving both power savings and maintained access speed for critical data.
2Speed
If tiles are kept in high power states for fast access, then access speed is maintained, but power consumption increases due to leakage current
Solution Approach 1:
The power state of each tile is dynamically adjusted based on real-time access frequency monitoring. The system continuously evaluates data access patterns and transitions tiles between high-power and low-power states accordingly, achieving adaptive balance between access speed and power consumption.
Solution Approach 2:
The power consumption parameter of tiles is changed based on access frequency thresholds. When access frequency falls below a threshold, the tile transitions to a low-power state with different electrical parameters (reduced voltage/current), thereby reducing leakage current while maintaining the capability for fast access when needed.
3Use of energy by moving object
If data is rearranged to group high and low access frequency data separately, then power consumption is reduced, but device complexity increases due to defragmentation operations
Solution Approach 1:
Data is pre-arranged into high-access-frequency and low-access-frequency groups before being written to tiles. This preliminary organization eliminates the need for complex runtime defragmentation operations, reducing device complexity while still enabling effective power management through selective tile power states.
Data Source
AI summary
A memory system (100) includes a memory (2) including a plurality of pages (21) on each of which data can be arranged and a defragmenting device (4) that rearranges the data arranged on the plurality of pages (21). The memory (2) includes a plurality of tiles (22) each including one or more pages. Each of the plurality of tiles (22) is configured to be capable of transitioning among a plurality of states in which power consumption suppression rates are different. The plurality of states include a low power consumption state different from a power-off state. The defragmenting device (4) rearranges the data such that the tile (22) in which high access frequency data are collected and the tile (22) in which low access frequency data are collected are present.