Access Buffer Reorders Memory Requests to Optimize Bandwidth
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Solution Overview
Problem
Existing memory controllers for DRAM systems face challenges in optimizing memory bandwidth utilization and minimizing latency while preventing logical errors due to reordering of read and write requests, and they lack fair sharing of memory bandwidth and prioritization of low-latency requests.
Innovation Solution
An access buffer system with write and read FIFO queues, a search unit, an access scheduler, and an arbiter that cancels pending write requests for read requests, ensuring data integrity and optimizing memory interface utilization by reordering requests to maintain correct transaction ordering and prioritize low-latency requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If read and write requests are reordered to optimize memory bandwidth utilization, then memory interface utilization is improved, but logical errors may occur due to incorrect transaction ordering
Solution Approach 1:
The patent segments requests into different priority levels (high-priority low-latency requests and normal-priority requests) and processes them separately through different FIFO queues. This segmentation allows the system to reorder requests for optimization while maintaining correct ordering within each segment, thus preventing logical errors while improving overall bandwidth utilization.
Solution Approach 2:
The patent introduces an access buffer as an intermediary component between the memory controller and DRAM. This buffer contains multiple FIFO queues (first FIFO for high-priority requests, second FIFO for normal-priority requests) that mediate the reordering process. The buffer allows requests to be reordered for optimization while maintaining transaction correctness through its structured queue management and arbitration logic.
2Reliability
If requests are processed in FIFO order to maintain transaction correctness, then logical errors are prevented, but memory bandwidth utilization is reduced
Solution Approach 1:
The patent implements dynamic request processing by allowing high-priority low-latency requests to bypass the normal FIFO ordering and be processed immediately when available. The arbitration logic dynamically selects between the first FIFO (high-priority) and second FIFO (normal-priority) based on request characteristics, enabling the system to adaptively optimize bandwidth utilization while maintaining correctness for time-sensitive operations.
Solution Approach 2:
The patent changes the processing parameter of request priority by categorizing requests into different priority levels. High-priority requests are assigned to the first FIFO queue and can be processed out of strict FIFO order relative to normal-priority requests, while normal-priority requests maintain FIFO ordering in the second queue. This parameter change enables flexible reordering that improves bandwidth without compromising correctness.
3Loss of time
If multiple FIFO queues are used to prioritize low-latency requests, then latency is minimized, but device complexity increases
Solution Approach 1:
The access buffer is segmented into multiple FIFO queues (first FIFO for high-priority requests, second FIFO for normal-priority requests) with dedicated arbitration logic for each queue. This segmentation enables the system to handle low-latency requests separately from normal requests, minimizing latency for time-sensitive operations while keeping the complexity manageable through clear separation of concerns and dedicated processing paths.
Data Source
AI summary
The disclosed embodiments relate to a system for controlling accesses to one or more memory devices. This system includes one or more write queues configured to store entries for write requests, wherein a given entry for a write request includes an address and write data to be written to the address. The system also includes a search mechanism configured to receive a read request which includes an address, and to search the one or more write queues for an entry with a matching address. If a matching address is found in an entry in a write queue, the search mechanism is configured to retrieve the write data from the entry and to cancel the associated write request, whereby the read request can be satisfied without accessing the one or more memory devices.