Access Control Cache for Memory Protection Systems
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Solution Overview
Problem
Existing data processing systems with hierarchical memory protection units face a processing bottleneck due to the complexity of determining access control data for memory addresses, leading to computationally intense operations when identifying the controlling region for memory access requests.
Innovation Solution
Implementing an access control cache that stores and provides access control data in place of memory protection circuitry, along with cachability signals to determine eligible data storage, reducing the need for frequent look-ups in memory protection circuitry and enhancing processing speed and energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If hierarchical ordering with overlapping regions is used to define memory access control, then memory address space partitioning flexibility is improved, but access control data lookup complexity increases
Solution Approach 1:
The system pre-determines and caches the controlling region for each memory address before actual memory access occurs. When a memory address is accessed, the pre-computed controlling region information is retrieved from the cache, eliminating the need for complex hierarchical region matching at access time. This preliminary computation and caching approach resolves the contradiction by maintaining flexible hierarchical region definitions while simplifying the actual access control lookup process.
2Reliability
If all access control data is stored in memory protection circuitry, then comprehensive access control is improved, but processing speed deteriorates
Solution Approach 1:
The access control data is segmented into two parts: the complete hierarchical region definitions remain in the memory protection circuitry for comprehensive control, while frequently accessed controlling region information is extracted and cached separately in a dedicated cache structure. This segmentation allows the system to maintain comprehensive access control while achieving faster processing speeds through the cache for routine lookups.
Solution Approach 2:
A cache structure acts as an intermediary between the memory protection circuitry and the memory access requests. The cache stores pre-determined controlling region information that mediates between the complex hierarchical region definitions and the simple address lookup requirement, providing fast access control decisions without sacrificing the comprehensiveness of the hierarchical protection scheme.
3Measurement precision
If complex hierarchical region matching is performed for each memory access, then access control precision is improved, but energy consumption increases
Solution Approach 1:
The controlling region for each memory address is pre-determined and cached before actual memory access occurs. This preliminary computation eliminates the need for repeated complex hierarchical region matching during normal operation, significantly reducing energy consumption while maintaining precise access control through the cached region information.
Data Source
AI summary
A data processing system (2) includes memory protection circuitry (10) storing access control data for controlling accesses to data at memory addresses within a main memory (16). An access control cache (14) may, in one embodiment, store access control data when the access control data is indicated by the memory protection circuitry (10) to be cachable. In another embodiment access control data is stored within the access control cache with determined address range data for reach determination of access control data by the memory protection circuitry. If the access control cache (14) is storing access control data for a memory access request, then the access control data stored within the access control cache (14) is used in place of access control data retrieved form the memory protection circuitry (10). In the first embodiment, access control data may be determined to be cachable is if is associated with a region of memory addresses within a plurality of hierarchically ordered memory addresses that is a highest order region which encompasses all the memory addresses within that region.