Access Enablement Circuit for SoC Security Control
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Solution Overview
Problem
System-on-chip (SoC) security features are vulnerable due to exposed interfaces, which can be exploited by malicious users to access internal components and data, lacking effective access control mechanisms.
Innovation Solution
A centralized access enablement circuit manages security features across multiple hardware modules, utilizing an access enablement table to establish different access control settings based on progressive security states, with one-time programmable memory and register controls, automatically generating a hardware description to reduce errors and enhance security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If interfaces are exposed for testing and evaluation, then ease of operation is improved, but security is worsened due to vulnerability to malicious access
Solution Approach 1:
The patent segments the interface access control by dividing security features into multiple discrete controllable elements. The access enablement circuit separates different security features and allows independent control of each feature's accessibility during testing and evaluation, enabling selective exposure of only necessary interfaces while keeping critical security functions protected.
Solution Approach 2:
The access enablement circuit acts as an intermediary between the exposed interfaces and the internal security features. It mediates access requests by controlling enablement signals to specific security features, allowing authorized testing and evaluation access while blocking unauthorized malicious access attempts.
2Object-affected harmful factors
If centralized access control is implemented, then security is improved, but device complexity increases due to additional control circuits
Solution Approach 1:
The access enablement circuit is designed with multi-functionality to control multiple different security features through a single unified circuit. This universal control mechanism reduces overall device complexity by consolidating what would otherwise require multiple separate control circuits for each security feature, while still providing centralized security management.
Solution Approach 2:
The patent merges the control logic for multiple security features into a single access enablement circuit. By combining individual control mechanisms into one unified circuit that can selectively enable/disable multiple security features, the design reduces circuit complexity while maintaining comprehensive centralized access control.
3Object-affected harmful factors
If individual access control settings are provided for each security feature, then security is improved, but device complexity increases due to multiple control settings
Solution Approach 1:
The access enablement circuit implements dynamic control settings that can be adjusted based on operational mode. During testing and evaluation modes, the circuit dynamically enables specific security features while maintaining individual control over each feature. This dynamic approach allows flexible individual control without requiring permanent complex control structures for all possible scenarios.
Data Source
AI summary
A system-on-chip (SoC) is provided that includes a centralized access enablement circuit for controlling access to a plurality of security features for multiple hardware modules of the system. Progressive security states corresponding to different stages in a chip's design, manufacture and delivery are utilized to enable different access control settings for security features as a part moves from design to end-use. The access enablement circuit for a SoC implementing different security states provides individual access control settings for security features in the different security states. One-time programmable memory and register controls are provided in one embodiment that allow different access control settings for an individual security feature in the same or different security states of the system.


