Access Line Capacitance and Resistance Determination in Memory Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Variabilities in the fabrication of memory devices lead to inconsistencies in operational parameters, making it challenging to determine accurate capacitive and resistive characteristics of access lines in memory devices, which affects their performance and reliability.
Innovation Solution
A method is introduced to determine the capacitive and resistive characteristics of access lines by applying a reference current and measuring voltage levels and time differences, using a distributed RC model to estimate capacitance and resistance values, allowing for more precise calibration of operational parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fabrication processes are used to manufacture memory devices, then production efficiency is improved, but variability in operational parameters increases
Solution Approach 1:
The patent applies parameter changes by systematically varying operational parameters (voltage levels, timing characteristics) during testing and calibration phases. This allows the memory device to be adjusted to compensate for fabrication variabilities, achieving consistent operational results despite manufacturing tolerances.
Solution Approach 2:
The patent implements feedback through iterative testing and calibration processes. Operational parameters are measured during testing, and adjustments are made based on these measurements until desired operating characteristics are achieved. This closed-loop approach compensates for fabrication variations.
2Measurement precision
If iterative testing and parameter adjustment is performed to achieve desired operating characteristics, then operational precision is improved, but time consumption increases
Solution Approach 1:
The patent applies preliminary action by performing systematic testing with initial parameter sets before final calibration. This structured approach pre-identifies key adjustment areas, reducing the number of iterative cycles needed for final optimization and thereby reducing total calibration time.
3Device complexity
If fabrication variabilities are not compensated for, then manufacturing complexity is reduced, but device reliability decreases
Solution Approach 1:
The patent uses parameter changes to compensate for fabrication variabilities by adjusting voltage levels, timing characteristics, and other operational parameters during calibration. This ensures reliable operation across different memory devices despite manufacturing tolerances.
Solution Approach 2:
The patent implements feedback mechanisms where testing results inform parameter adjustments, which are then validated through subsequent testing. This iterative feedback process ensures that reliability targets are met while managing calibration complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more accurate determination of operational parameters, improving the reliability and performance of memory devices by accounting for variabilities in fabrication, leading to consistent and efficient memory access operations.
Implementation Method 1
a capacitance value of the selected access line is determined in response to a current level of the reference current, a time difference between the first event and the second event, and a voltage difference between the first voltage level and the second voltage level
Implementation Method 2
a resistance value of the selected access line is determined in response to a current level of the reference current, and a voltage difference between the particular voltage level and the resting voltage level
Data Source
AI summary
Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to determine capacitance and/or resistance values of an access line in response to applying a reference current to the access line, wherein the access line is connected to control gates of memory cells of the array of memory cells.