Access-Based Memory Refresh Control for Lower Downtime
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAM, face downtime and increased power consumption due to the need for frequent refresh operations to maintain data integrity, which makes them unavailable for access operations.
Innovation Solution
Implementing background refresh operations that allow refreshes to occur concurrently with access operations, reducing the number of stand-alone refreshes by using a refresh deficit count to determine when and how to perform refreshes, and employing a controller to manage refresh commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed to maintain data integrity in DRAM memory cells, then data integrity is preserved, but the memory device becomes unavailable for access operations causing downtime
Solution Approach 1:
The patent performs refresh operations in advance during access operations on different banks. The refresh control circuit monitors access operations and proactively initiates background refreshes on non-accessed banks before data degradation becomes critical, ensuring data integrity is maintained while minimizing disruption to ongoing access operations.
Solution Approach 2:
The patent implements continuous background refresh operations that run concurrently with access operations. By continuously monitoring bank states and performing refreshes during idle periods within access operations, the system maintains uninterrupted data integrity preservation without complete shutdown of memory access functionality.
2Reliability
If frequent refresh operations are performed to maintain data integrity, then data integrity is preserved, but power consumption increases
Solution Approach 1:
The patent performs refresh operations only on specific banks that require refreshing, rather than all banks simultaneously. The refresh control circuit determines which banks need refresh based on access patterns and performs partial refreshes during access operations on other banks, reducing overall power consumption while maintaining data integrity where needed.
Solution Approach 2:
The patent implements periodic background refresh operations interspersed with access operations. Instead of continuous high-power refreshes, the system periodically performs refreshes during naturally occurring access operation windows, reducing average power consumption while ensuring data integrity is maintained through regular refresh cycles.
3Reliability
If stand-alone refresh operations are performed, then data integrity is maintained, but the number of unavailable memory periods increases
Solution Approach 1:
The patent merges refresh operations with access operations by performing background refreshes on non-accessed banks during access operations. The refresh control circuit combines the timing and resource utilization of both operation types, allowing refresh and access to occur simultaneously on different banks, thereby eliminating separate stand-alone refresh periods and improving overall productivity.
Solution Approach 2:
The patent adds a temporal dimension to refresh operations by executing them in parallel with access operations on different banks. This dimensional approach to resource allocation allows the memory system to maintain data integrity through refresh while simultaneously maintaining access productivity, effectively resolving the contradiction between reliability and productivity.
Data Source
AI summary
A memory device receives a command, address, or combination thereof as part of an access operation which indicates an opportunity to perform a refresh background operation. The memory device may determine whether or not to perform the background refresh operation. If a background refresh operation is performed, the memory accesses a word line in a first section of a memory bank and refreshes a word line in a different section of the memory bank. In some embodiments, an opportunity background refresh operation may be signaled by an access command with an extended timing window.