Access Triggered Architecture Pipelining for Time-Critical Operations

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

General purpose processors experience high failure rates in time-critical operations, such as engine control, due to their inability to provide precise timing, leading to inefficiencies and potential collisions.

Innovation Solution

An access triggered computer architecture system that executes operations based on execution time, utilizing a pipeline to reduce execution time by creating a system with a processor, system memory, and functional blocks, where each block performs operations using datasets and instruction sets with source and destination pointers to relocate data and trigger operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If general purpose processors are used for time-critical operations, then versatility is maintained, but reliability deteriorates due to high failure rates and inability to provide precise timing

Engineering Contradiction:
ImprovereliabilityVSAvoidversatility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The processor is divided into multiple functional blocks, each dedicated to specific time-critical operations. This segmentation allows each block to be optimized for its specific function while maintaining overall system versatility through the combination of multiple specialized blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system achieves versatility through multiple functional blocks that can be configured for different operations. Each block can handle specific operation types, and the combination of blocks provides universal processing capability while maintaining precise timing for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If traditional sequential execution is used, then simplicity is maintained, but productivity deteriorates due to longer execution times

Engineering Contradiction:
ImproveproductivityVSAvoidcomplexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system implements pipelining where multiple operations overlap in execution. While one operation is being executed in a functional block, another operation can be prepared in the instruction queue, and a third can be fetched from memory. This continuous overlapping of operations increases productivity without requiring complex coordination between sequential steps.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The instruction queue pre-loads and prepares instructions before they are needed for execution. This preliminary action allows the system to have instructions ready in the queue while functional blocks are executing previous operations, reducing waiting time and increasing overall productivity.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If execution time is reduced through pipelining, then productivity improves, but reliability worsens due to potential timing errors and data corruption

Engineering Contradiction:
Improveexecution speedVSAvoiddata integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system incorporates error detection and correction mechanisms that provide feedback on data integrity. Error correction codes are calculated and verified, and any timing errors or data corruption detected during pipelined execution are corrected, maintaining reliability while allowing high-speed parallel operations.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

Error correction codes are calculated and prepared in advance before data is transmitted or processed. This preliminary error protection cushioning allows the system to detect and correct errors that may occur during high-speed pipelined execution, maintaining data integrity despite reduced execution times.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS10353681B2Systems and methods for using error correction and pipelining techniques for an access triggered computer architecture
Publication Date: 2019.07.16 HONEYWELL INTERNATIONAL INC
  • US10353681B2 patent drawing
  • US10353681B2 patent drawing
  • US10353681B2 patent drawing

AI summary

A method for improving performance of an access triggered architecture for a computer implemented application is provided. The method first executes typical operations of the access triggered architecture according to an execution time, wherein the typical operations comprise: obtaining a dataset and an instruction set; and using the instruction set to transmit the dataset to a functional block associated with an operation, wherein the functional block performs the operation using the dataset to generate a revised dataset. The method further creates a pipeline of the typical operations to reduce the execution time of the typical operations, to create a reduced execution time; and executes the typical operations according to the reduced execution time, using the pipeline.