Access Triggered Architecture Pipelining for Engine Control Timing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

General purpose processors experience high failure rates in time-critical operations, such as engine control, due to their inability to provide precise timing, leading to inefficiencies and potential collisions.

Innovation Solution

An access triggered computer architecture system with pipelining and error correction techniques is implemented, where each functional block performs arithmetic and logical operations on input datasets, and a pipeline is created to reduce execution time by overlapping operations across clock cycles, ensuring accurate and timely data processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If general purpose processors are used for time-critical operations, then versatility is maintained, but reliability deteriorates due to high failure rates and inability to provide precise timing

Engineering Contradiction:
Improveexecution reliabilityVSAvoidprocessor versatility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The processor is divided into multiple functional blocks, each dedicated to specific time-critical operations. This segmentation allows each block to be optimized for its particular function while maintaining overall system versatility through the combination of specialized blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different functional blocks are assigned different specialized qualities optimized for their specific operations. Each block has tailored hardware resources and execution mechanisms suited to its function, improving reliability for time-critical tasks while the collection of diverse blocks maintains system versatility.

Inventive Principle:
Principle #3Local quality

2Productivity

If sequential execution is used in access triggered architecture, then simplicity is maintained, but productivity deteriorates due to longer execution time

Engineering Contradiction:
Improveexecution speedVSAvoidarchitecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The architecture pre-loads instructions and data into buffer memory before they are needed for execution. This preliminary action allows the functional blocks to immediately process available data without waiting for memory access, significantly improving execution speed while adding only moderate complexity through buffer management.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically switches between sequential and parallel execution modes based on operational requirements. The control logic adapts the execution flow to maximize productivity for time-critical operations while maintaining simplicity for less demanding tasks.

Inventive Principle:
Principle #15Dynamics

3Productivity

If parallel execution is implemented to reduce execution time, then productivity improves, but reliability worsens due to increased complexity and potential for errors

Engineering Contradiction:
Improveexecution speedVSAvoidsystem reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system uses periodic clock cycles to synchronize parallel operations across functional blocks. Each block executes operations in regular intervals, and the control logic coordinates data flow between blocks at these periodic intervals, maintaining reliability through synchronization while achieving parallel productivity gains.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The architecture implements feedback mechanisms where the control logic monitors the execution state of parallel operations and adjusts data flow and timing accordingly. This feedback ensures that parallel execution maintains data integrity and timing requirements, preserving reliability while achieving high productivity.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP3460654B1Systems and methods for using error correction and pipelining techniques for an access triggered computer architecture
Publication Date: 2023.04.12 HONEYWELL INTERNATIONAL INC
  • EP3460654B1 patent drawingFigure 1
  • EP3460654B1 patent drawingFigure 2
  • EP3460654B1 patent drawingFigure 3

AI summary

A method for improving performance of an access triggered architecture for a computer implemented application is provided. The method first executes typical operations of the access triggered architecture according to an execution time, wherein the typical operations comprise: obtaining a dataset and an instruction set; and using the instruction set to transmit the dataset to a functional block associated with an operation, wherein the functional block performs the operation using the dataset to generate a revised dataset. The method further creates a pipeline of the typical operations to reduce the execution time of the typical operations, to create a reduced execution time; and executes the typical operations according to the reduced execution time, using the pipeline.