Accumulate Coding with Interleavers for Low-Complexity Decoding
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Solution Overview
Problem
Current channel coding techniques, such as turbo codes and LDPC codes, face challenges in high computational complexity and memory requirements, particularly in high-speed wireless communication and portable devices, which can lead to increased latency and impractical memory usage.
Innovation Solution
The proposed solution involves a system that uses a feedforward convolutional outer code encoder and a rate-1 1/(1+D) accumulate code based inner code encoder, along with interleavers, to generate encoded bits and codewords, and a decoder that processes log-likelihood ratios through iterative decoding, reducing complexity and memory needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If turbo codes or LDPC codes are used to achieve near-capacity performance, then error correction capability is improved, but computational complexity and memory requirements increase
Solution Approach 1:
The patent segments the coding system into an outer code (convolutional or block code) and an inner accumulate code, where each segment has simpler individual complexity but together they achieve near-capacity performance. The outer encoder processes information bits separately from the inner encoder processing the outer codeword, dividing the computational burden.
Solution Approach 2:
The patent changes the code structure parameters by using a specific accumulate code with generator polynomial 1/(1+D) and carefully designed interleaving patterns, transforming the overall system complexity while maintaining near-capacity performance. The accumulate code rate-1 1/(1+D) provides a balance between complexity and performance.
2Reliability
If iterative decoding is used for turbo codes or LDPC codes, then error correction performance is improved, but decoding latency increases
Solution Approach 1:
The iterative decoding process is segmented into outer decoding and inner decoding stages, where the outer decoder first processes the received signal to produce extrinsic information, which is then interleaved and processed by the inner decoder. This segmentation allows for optimized iteration schemes that reduce overall latency while maintaining performance.
3Device complexity
If product accumulate codes are used to reduce computational complexity, then encoding complexity is reduced, but memory requirements for interleavers increase
Solution Approach 1:
The patent changes the interleaver memory size parameter by using a specific interleaving pattern that is a function of the block length and code rate, optimizing the balance between computational complexity and memory requirements. The accumulate code structure with rate-1 1/(1+D) provides a favorable trade-off.
4Reliability
If large interleaver memory is used for product accumulate codes, then near-capacity performance is achieved, but memory usage becomes impractical for portable devices
Solution Approach 1:
The patent optimizes the interleaver memory size by carefully selecting the interleaving pattern parameters as functions of block length and code rate, achieving near-capacity performance with practical memory sizes suitable for portable devices. The accumulate code structure enables this optimization.
Data Source
AI summary
An encoder for use in information processing applications includes an input configured to provide information bits to be encoded and a feedforward convolutional outer code encoder configured to encode the information bits to generate encoded information bits including the information bits and parity bits. The encoder may also include at least one interleaver configured to interleave the encoded information bits to generate an outer codeword. Further, the encoder may include a rate-1 1/(1+D) accumulate code based inner code encoder configured to encode the outer codeword to generate one or more codewords corresponding to the information bits.