Convolution Core Accumulation Buffer Layout for Low-Power MAC
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Solution Overview
Problem
Existing systems for multiply/accumulate operations, such as neural networks and matrix multiplication, face inefficiencies in power consumption and memory usage, particularly in long accumulation sequences.
Innovation Solution
Implementing a 32-bit accumulation buffer with regions A, B, and C, where regions A and B are within the convolution core and region C is stored in shared memory, along with a clock disabling mechanism to reduce power consumption, and using a sequencer or FIFO buffer for data management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If extensive accumulation buffers are used to support combine multiple groups of data, then data processing capability is improved, but power consumption and memory requirements increase
Solution Approach 1:
The accumulation buffer is divided into multiple regions (first region, second region, third region) that can be independently managed. This segmentation allows the system to activate only the necessary regions for current operations, reducing overall power consumption while maintaining the capability to process multiple groups of data efficiently.
Solution Approach 2:
The system dynamically activates or deactivates specific regions of the accumulation buffer based on operational requirements. By making the buffer regions dynamically controllable, the system adapts power consumption to actual processing needs, improving energy efficiency without sacrificing data processing capability when full capacity is required.
2Productivity
If extensive accumulation buffers are used to support combine multiple groups of data, then data processing capability is improved, but memory requirements increase
Solution Approach 1:
The accumulation buffer is segmented into multiple regions that can be independently activated. This allows the system to use only the necessary memory regions for current operations, effectively reducing the active memory footprint while maintaining the potential capacity to handle multiple data groups when all regions are activated.
Solution Approach 2:
The divided accumulation buffer regions serve multiple purposes - each region can handle different data groups independently, and regions can be selectively activated based on processing needs. This multi-functionality allows the same physical memory structure to support various data processing scenarios with optimized memory usage.
3Device complexity
If sequential data fetching is used, then system complexity is reduced, but processing speed decreases
Solution Approach 1:
By dividing the accumulation buffer into separate regions, the system can simultaneously access different regions for different data groups, enabling parallel data fetching operations. This segmentation transforms the sequential access model into a parallel access architecture, significantly improving data access speed while maintaining manageable system complexity through modular region management.
Solution Approach 2:
The system transitions from sequential one-dimensional data fetching to multi-dimensional parallel access by organizing data across multiple buffer regions. This dimensional change allows simultaneous access operations across different regions, effectively adding a parallelism dimension to the data fetching process without overly complicating the control logic.
Data Source
AI summary
Example accumulation systems and methods are described. In one implementation, data is received for processing. A multiplication operation is performed on the received data to generate multiplied data. An addition operation is performed on the multiplied data to generate a result. At least a portion of the least significant bits of the result are stored in a first region of an accumulation buffer of a convolution core. And, at least a portion of the remaining bits of the result are stored in a shared memory that is separate from the convolution core.