Accumulation-Mode FET Structure for Breakdown-Resistant Scaling
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Solution Overview
Problem
Semiconductor devices with smaller channel lengths experience heightened levels of device failures due to hot carrier injection (HCI), time-dependent dielectric breakdown (TDDB), and bias temperature instability (BTI), exacerbated by thin gate dielectric layers and increased electrical fields.
Innovation Solution
Employing accumulation mode field effect transistors (FETs) with a single dopant type in the channel, source, and drain, and adjusting dopant concentrations and work function layers to reduce vertical and lateral field strengths, thereby minimizing carrier density at the gate dielectric interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If thin gate dielectric layers are used to reduce short channel effects, then device scaling is improved, but aging-related breakdown (HCI, TDDB, BTI) increases due to high electrical fields at the gate dielectric-channel interface
Solution Approach 1:
The patent changes the electrical field parameter by using accumulation mode FETs with a single dopant type in channel, source, and drain regions, combined with a work function layer difference between gate electrode and channel region. This reduces the vertical field strength across the gate dielectric layer, thereby reducing aging-related breakdown while maintaining thin gate dielectric layers for continued device scaling.
2Reliability
If conventional FET structures with opposite dopant types in channel and source/drain are used, then device performance is maintained, but high electrical fields at the gate dielectric-channel interface accelerate aging-related breakdown
Solution Approach 1:
The patent changes the doping configuration parameter from conventional opposite dopant types to a single dopant type in accumulation mode FETs. Combined with a work function layer difference, this reduces the vertical electrical field strength at the gate dielectric-channel interface, reducing harmful effects like hot carrier injection and dielectric breakdown while maintaining device performance.
Data Source
AI summary
A method of manufacturing a semiconductor device includes implanting a channel region of a first transistor and a channel region of a second transistor to have a first conductivity type. The method further includes forming source/drain regions of the first transistor to have the first conductivity type and source/drain regions of the second transistor to have a second conductivity type, wherein the second conductivity is different from the first conductivity type. The method further includes depositing a first work function layer over the channel region of the first transistor. The method further includes depositing a second work function layer over the channel region of the second transistor, wherein the first work function layer includes a same material as the second work function layer.