Accumulation Circuit Using Overlap Lanes to Prevent Overflow
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Solution Overview
Problem
Existing data processing systems face high power consumption during accumulation operations due to the need for large buffers to accommodate addends with varying magnitudes, leading to potential information loss and increased power usage.
Innovation Solution
Storing the second addend across multiple lanes with varying significance, each containing overlap bits, allows the accumulation operation to be performed within a single lane without overflowing, reducing the need to access multiple buffers and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If large buffers are used to accommodate addends with varying magnitudes, then information loss is prevented, but power consumption increases
Solution Approach 1:
The patent divides the buffer into multiple lanes with different significances (first lane, second lane, third lane, etc.), where each lane stores bits of the second addend with a specific significance range. This segmentation allows the system to access only the necessary lane for each accumulation operation rather than accessing a single large buffer, thereby reducing power consumption while preventing information loss through overflow.
2Use of energy by moving object
If single lane is used for accumulation operations, then power consumption is reduced, but overflow may occur
Solution Approach 1:
The patent introduces an additional dimension of lane significance to solve the overflow problem. When an accumulation operation is performed in a given lane and overflow occurs, the system can transfer the overflowed bits to a more significant lane (e.g., from second lane to first lane). This dimensional approach allows the system to maintain reliability by preventing information loss while keeping power consumption low by operating primarily within a single lane.
3Reliability
If multiple buffers are accessed for accumulation operations, then overflow is prevented, but device complexity increases
Solution Approach 1:
The patent segments the buffer into multiple lanes with hierarchical significance levels, where each lane handles a specific range of bit significances. This structured segmentation provides a systematic approach to preventing overflow while managing device complexity through organized bit distribution across lanes, making the system more manageable compared to using multiple independent buffers.
Data Source
AI summary
An apparatus has processing circuitry to perform an accumulation operation in which a first addend is added to a second addend. The apparatus has storage circuitry to store the second addend in a plurality of lanes, each lane having a significance different to that of each other lane. Each lane within at least a subset of the lanes comprises at least one overlap bit having the same bit significance as a bit in an adjacent more significant lane in the plurality of lanes. The accumulation operation includes selecting an accumulating lane out of the plurality of lanes and performing an addition operation between bits of the accumulating lane and the first addend. The at least one overlap bit of the accumulating lane enables the addition operation to be performed without a possibility of overflowing the accumulating lane.