Accumulator Hardware Logic for Varying Bit-Width Convolution
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Solution Overview
Problem
Convolutional neural networks require large hardware implementations for performing numerous multiplications of input values and filter weights, leading to significant area and power consumption, especially when bit-widths vary, resulting in inefficient use of resources.
Innovation Solution
The implementation of accumulator hardware logic with shifting and negation hardware in a feedback path allows for efficient accumulation and multiplication operations over multiple clock cycles, reducing hardware size and power consumption by performing operations on varying bit-widths and optimizing gate-level synthesis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dedicated hardware logic is used to perform large numbers of multiplications for convolutional neural networks, then the speed of operation is increased, but the hardware area and power consumption become significant
Solution Approach 1:
The patent segments the multiplication operation into two phases: a first phase using a first multiplier and a second phase using a second multiplier. This segmentation allows the hardware to perform multiplication operations across multiple clock cycles rather than requiring a single complex multiplier, thereby reducing the hardware area while maintaining computational speed.
Solution Approach 2:
The patent employs dynamic switching between different multipliers based on the bit-width requirements of the input values. The controller dynamically selects which multiplier to use (first or second) depending on the operational requirements, allowing the hardware to adapt its configuration and optimize the balance between speed and area utilization.
2Speed
If dedicated hardware logic is used to perform large numbers of multiplications for convolutional neural networks, then the speed of operation is increased, but power consumption becomes significant
Solution Approach 1:
The patent segments the multiplication operation into two phases: a first phase using a first multiplier and a second phase using a second multiplier. This segmentation allows the hardware to perform multiplication operations across multiple clock cycles rather than requiring a single complex multiplier, thereby reducing the hardware area while maintaining computational speed.
Solution Approach 2:
The patent employs dynamic switching between different multipliers based on the bit-width requirements of the input values. The controller dynamically selects which multiplier to use (first or second) depending on the operational requirements, allowing the hardware to adapt its configuration and optimize the balance between speed and area utilization.
3Device complexity
If fixed bit-width hardware is used for multiplication operations, then the hardware design is simplified, but it cannot efficiently handle varying bit-widths resulting in inefficient resource use
Solution Approach 1:
The patent designs a universal multiplication hardware structure that can handle multiple bit-widths (e.g., 4-bit, 8-bit, 16-bit) using the same basic architecture with two multipliers. The controller manages the selection and configuration of multipliers based on the required bit-width, making the hardware versatile without requiring separate dedicated circuits for each bit-width scenario.
Solution Approach 2:
The patent employs dynamic switching between different multipliers based on the bit-width requirements of the input values. The controller dynamically selects which multiplier to use (first or second) depending on the operational requirements, allowing the hardware to adapt its configuration and optimize the balance between speed and area utilization.
Data Source
AI summary
Accumulator hardware logic includes first and second addition logic units and a store. The first addition logic unit comprises a first input, a second input and an output, each of the first and second inputs arranged to receive an input value in each clock cycle. The second addition logic unit comprises a first input that is connected directly to the output of the first addition logic unit. It also comprises a second input and an output. The store is arranged to store a result output by the second addition logic unit. The accumulator hardware logic further comprises shifting hardware and/or negation hardware positioned in a feedback path between the store and the second input of the second addition logic unit. The shifting hardware is configured to perform a shift by a fixed number of bit positions in a fixed direction.