Accumulator Latch Circuit for High-Speed MAC Operations
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Solution Overview
Problem
In deep learning applications, the speed of the accumulation operation in accumulators often lags behind the input data speed, reducing the overall performance of multiplication-accumulation (MAC) operations.
Innovation Solution
The proposed solution involves an accumulator design with an input latch circuit, an accumulating circuit, and an output latch circuit, which includes multiple latches and adders to manage and synchronize data inputs and outputs, ensuring efficient handling of odd and even latch data to enhance accumulation operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional accumulator design is used, then the structure is simple, but the accumulation operation speed is slower than the data input speed
Solution Approach 1:
The accumulator is divided into multiple independent latch circuits (first input latch, second input latch, third input latch, first output latch, second output latch) that operate in parallel. Each latch handles specific data paths (input data, odd latch data, even latch data), enabling simultaneous data processing and accumulation operations, thereby increasing accumulation speed without proportionally increasing overall system complexity.
Solution Approach 2:
Data is pre-latched in the input latch circuits before being fed into the accumulating circuit. The first input latch latches input data, while the second and third input latches prepare odd and even latch data in advance. This preliminary data preparation ensures that when accumulation operations are needed, the data is already ready and synchronized, eliminating waiting time and speeding up the accumulation process.
2Productivity
If data is processed sequentially, then the device complexity is low, but the overall MAC operation speed is reduced
Solution Approach 1:
The data processing path is segmented into multiple parallel channels: one path handles input data through the first input latch, while separate paths handle odd latch data through the second input latch and even latch data through the third input latch. The accumulating circuit simultaneously processes these segmented data streams, enabling parallel MAC operations and significantly increasing throughput.
Solution Approach 2:
The latch circuits are designed to operate continuously without idle periods. While the first input latch is loading new input data, the second and third input latches are simultaneously preparing odd and even latch data from previous operations. The accumulating circuit continuously receives synchronized data from all latches, ensuring uninterrupted MAC operations and maximizing productivity.
Data Source
AI summary
An accumulator includes an input latch circuit including a first input latch capable of latching and outputting input data, a second input latch capable of latching and outputting odd latch data, and a third input latch capable of latching and outputting even latch data. The accumulator also includes an accumulating circuit configured to add the input data and the odd latch data output from the input latch circuit to output odd accumulation data, and configured to add the input data and the even latch data to output even accumulation data. The accumulator further includes an output latch circuit including a first output latch capable of latching the odd accumulation data output from the accumulating circuit and outputting the odd latch data, and including a second output latch capable of latching the even accumulation data output from the accumulating circuit and outputting the even latch data.