Accumulator Logic Circuit for Multi-Core Server Load Balancing

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Solution Overview

Problem

In multi-core/multi-blade server load balancing systems, the exchange of IPC messages or IP packets between CPU cores and the central core processor for aggregating local counter values consumes significant CPU resources, leading to processing delays and inefficient memory usage, especially as the number of CPU cores increases.

Innovation Solution

A hardware-based load balancer with accumulator logic circuits on each blade aggregates local counter values, with a master accumulator logic circuit transmitting global counter values to the management processor and CPU cores, reducing the management processor's processing and memory requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If software-based aggregation of local counter values is used in multi-core systems, then load balancing functionality is achieved, but CPU resource consumption increases and processing delays occur

Engineering Contradiction:

Improveload balancing accuracyVSAvoidCPU resource consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent replaces the software-based counter aggregation mechanism with a hardware-based accumulator circuit implemented in ASIC logic. This substitution moves the aggregation function from the CPU software environment to dedicated hardware, eliminating the need for IPC messages and software processing, thereby resolving the contradiction between load balancing accuracy and CPU resource consumption.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The accumulator circuit is designed to autonomously aggregate local counter values from multiple CPU cores without requiring intervention from the management processor or central coordination. Each accumulator circuit self-manages the collection and aggregation of counter data, freeing CPU resources while maintaining accurate load balancing information.

Inventive Principle:

Principle #25Self-service

2Measurement precision

If local counter values are aggregated via IPC messages between CPU cores and central processor, then global counter values are obtained, but processing delays increase

Engineering Contradiction:

Improveglobal counter accuracyVSAvoidaggregation delay

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent replaces the software-based IPC message passing mechanism with direct hardware connections between CPU cores and the accumulator circuit. This hardware pathway eliminates the serialization and processing delays inherent in software-based IPC communication, enabling real-time aggregation of counter values without sacrificing accuracy.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The accumulator circuit continuously aggregates counter values in real-time rather than waiting for periodic software updates. This continuous hardware-based accumulation ensures that global counter values are always current, eliminating the time lag associated with periodic software polling and message exchange.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If central core processor stores copies of all local counter values, then complete statistics are maintained, but memory usage increases inefficiently

Engineering Contradiction:

Improvestatistics completenessVSAvoidmemory capacity

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts the counter storage and aggregation function from the central management processor's memory space and places it in dedicated hardware accumulators. This extraction eliminates the need for the management processor to allocate large memory buffers for storing all local counter values, while the aggregated results remain available for load balancing decisions.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges all local counter values into a single aggregated global counter value through the hardware accumulator circuit. This consolidation reduces the total data storage requirement from multiple individual counter copies to a single aggregated value, significantly reducing memory usage while maintaining the reliability needed for load balancing.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9411656B2Load balance connections per server in multi-core/multi-blade system

Publication Date: 2016.08.09 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

A network device includes a plurality of blades, each having a plurality of CPU cores that process requests received by the network device. Each blade further includes an accumulator circuit. Each accumulator circuit periodically aggregates the local counter values of the CPU cores of the corresponding blade. One accumulator circuit is designated as a master, and the other accumulator circuit(s) are designated as slave(s). The slave accumulator circuits transmit their aggregated local counter values to the master accumulator circuit. The master accumulator circuit aggregates the sets of aggregated local counter values to create a set of global counter values. The master accumulator circuit transmits the global counter values to a management processor (for display), to the CPU cores located on its corresponding blade, and to each of the slave accumulator circuits. Each slave accumulator circuit then transmits the global counter values to the CPU cores located on its corresponding blade.