Accuracy Configurable Approximate Adder with Dynamic Error Correction

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Solution Overview

Problem

Existing approximate adder designs are limited in their ability to dynamically adjust accuracy according to changing requirements, as they are typically optimized for a maximum accuracy threshold, which reduces their benefits in contexts where accuracy needs vary over time.

Innovation Solution

An accuracy-configurable approximate adder that can adaptively operate in both accurate and inaccurate modes, with error detection and correction capabilities, and a pipelined architecture that allows for selectable stages and power-gated error correction to conserve power and improve throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If approximate adder designs are optimized for maximum accuracy threshold, then accuracy is improved, but throughput and power consumption benefits are reduced

Engineering Contradiction:
ImproveaccuracyVSAvoidthroughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The adder design dynamically switches between approximate and accurate modes based on runtime accuracy requirements. The system includes configurable accuracy modes where the adder can operate in approximate mode for high throughput or switch to accurate mode when precision is required, making the performance characteristics adaptable rather than fixed

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the accuracy parameter of the adder runtime by configuring different accuracy modes. The adder can be set to produce results with different accuracy levels (e.g., 1-bit accuracy, 2-bit accuracy, or full accuracy) depending on the application requirements, allowing the system to optimize the accuracy-throughput tradeoff dynamically

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If approximate adder designs are optimized for maximum accuracy threshold, then accuracy is improved, but power consumption increases

Engineering Contradiction:
ImproveaccuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The adder design dynamically switches between approximate and accurate modes based on runtime accuracy requirements. The system includes configurable accuracy modes where the adder can operate in approximate mode for low power consumption or switch to accurate mode when precision is required, making the power consumption characteristics adaptable rather than fixed

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the accuracy parameter of the adder runtime by configuring different accuracy modes. The adder can be set to produce results with different accuracy levels (e.g., 1-bit accuracy, 2-bit accuracy, or full accuracy) depending on the application requirements, allowing the system to optimize the power consumption-accuracy tradeoff dynamically

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If error detection and correction is enabled, then accuracy is improved, but device complexity increases

Engineering Contradiction:
ImproveaccuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The adder is divided into multiple independent sub-adders that can be configured to different accuracy levels. Each sub-adder processes a specific portion of the input and can be enabled or disabled based on the required accuracy, allowing error correction to be applied selectively to only the necessary portions of the computation

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9229686B2Accuracy configurable adders and methods
Publication Date: 2016.01.05 RGT UNIV OF CALIFORNIA
  • US9229686B2 patent drawing
  • US9229686B2 patent drawing
  • US9229686B2 patent drawing

AI summary

A preferred method of accuracy configuration with an approximate adder receives two input operands and generates a first approximate adder output with a plurality of sub-adders having a first accuracy under a first condition. Error detection and correction is selectively enabled to generate a next approximate adder output having a second accuracy that is higher than the first accuracy under a second condition. In preferred embodiments, a pipelined architecture provides selectable stages and the enablement of each successive stage provides a high level of accuracy. Power gated control can achieve enablement of error correction stages to conserve power.