Acoustic Resonator Planarization Layer for Piezoelectric Defect Reduction
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Solution Overview
Problem
Conventional acoustic resonator fabrication methods often result in defects such as cracks and voids in the piezoelectric layer, leading to reduced breakdown voltage and increased susceptibility to electro-static discharge (ESD), due to the bottom electrode extending beyond the cavity edge, which affects the structural and operational stability of the device.
Innovation Solution
A method is introduced to fabricate acoustic resonators with a planarization layer of dielectric material adjacent to the bottom electrode, using an etch stop layer to create a planarized surface for the piezoelectric layer, which improves its structural and operational stability and increases the breakdown voltage by reducing defects like cracks and voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the bottom electrode extends beyond the cavity edge to provide structural support, then the structural stability is improved, but the piezoelectric layer develops defects such as cracks and voids due to the transition portion spanning two levels
Solution Approach 1:
The invention introduces a planarization layer that segments the transition portion of the piezoelectric layer, separating it into two distinct levels: a first portion over the bottom electrode and a second portion over the planarization layer. This segmentation eliminates the continuous transition spanning two levels, thereby preventing cracks and voids while maintaining the bottom electrode's structural support function.
Solution Approach 2:
The planarization layer acts as an intermediary element between the bottom electrode and the piezoelectric layer. It provides a planar surface for the piezoelectric layer's second portion, eliminating the need for the piezoelectric layer to directly span the transition from substrate to electrode surface, thus preventing defects.
2Reliability
If the piezoelectric layer spans a transition portion between two levels, then the bottom electrode can extend beyond the cavity, but the breakdown voltage is reduced due to increased susceptibility to electro-static discharge
Solution Approach 1:
By segmenting the piezoelectric layer into two portions separated by the planarization layer, the invention eliminates the薄弱 transition region that was susceptible to electro-static discharge. The piezoelectric layer's second portion now rests on a planar surface, distributing electrical stress uniformly and preventing charge accumulation that leads to breakdown.
Solution Approach 2:
The planarization layer serves as a protective cushioning layer deposited beforehand to prevent electro-static discharge damage. It provides a uniform dielectric barrier that cushions against electrical stress, preventing the piezoelectric layer from experiencing concentrated electrical fields that would cause breakdown.
3Manufacturing precision
If a planarization layer is added to create a planar surface for the piezoelectric layer, then the piezoelectric layer quality and breakdown voltage are improved, but the device complexity and fabrication steps increase
Solution Approach 1:
The planarization layer serves multiple functions simultaneously: it provides a planar surface for the piezoelectric layer, acts as an etch stop layer, and serves as a protective barrier against electro-static discharge. This multi-functionality reduces the need for separate layers, thereby minimizing the increase in device complexity while achieving improved piezoelectric layer quality.
Solution Approach 2:
The invention changes the physical and chemical parameters of the planarization layer (such as dielectric constant, thickness, and material composition) to optimize its performance in providing a planar surface while maintaining compatibility with existing fabrication processes. By carefully selecting these parameters, the planarization layer achieves defect reduction without requiring completely new fabrication methodologies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The planarized surface enhances the quality of the piezoelectric layer, reducing defects and improving the overall stability and ESD resistance of the acoustic resonator, leading to improved performance and reliability.
Implementation Method 1
forming an etch stop layer over the bottom electrode and the substrate; forming a dielectric layer on the etch stop layer over the bottom electrode and the substrate... etching a portion the dielectric layer through the opening of the photomask to the etch stop layer... removing the protruding portions of the dielectric layer, a portion of the etch stop layer located over the bottom electrode
Implementation Method 2
Where an input electrical signal is applied between the electrodes, reciprocal or inverse piezoelectric effect causes the acoustic stack to mechanically expand or contract depending on the polarization of the piezoelectric material
Implementation Method 3
As the input electrical signal varies over time, expansion and contraction of the acoustic stack produces acoustic waves that propagate through the acoustic resonator in various directions and are converted into an output electrical signal by the piezoelectric effect
Data Source
AI summary
A method is provided for fabricating a bulk acoustic wave (BAW) resonator device. The method includes forming an etch stop layer over a bottom electrode and a substrate; forming a dielectric layer on the etch stop layer; forming a photomask over the dielectric layer defining an opening over the bottom electrode; etching a portion the dielectric layer through the opening of the photomask to the etch stop layer to create a corresponding opening in the dielectric layer; removing the photomask, leaving un-etched protruding portions of the dielectric layer around the opening in the dielectric layer; and removing the protruding portions of the dielectric layer, a portion of the etch stop layer located over the bottom electrode, and a minimal portion of the bottom electrode to provide a planarized surface including a top surface of the bottom electrode and an adjacent top surface of the dielectric layer deposited over the substrate.