ACS Path Metric Circuit Using Redundant MSB Limiting
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Solution Overview
Problem
The existing ACS units in Viterbi decoders, which employ pipelining, look-ahead, and parallelism techniques to enhance computation speed and circuit performance, result in increased circuit complexity and manufacturing costs, necessitating a solution that minimizes circuit dimensions without degrading performance.
Innovation Solution
The implementation of a novel ACS unit with a first ACS circuit, a most significant bit-pair (MSB) ACS circuit, including a limiting circuit, MSB maximum select unit, MSB storage unit, and reset unit, which generates and processes path metrics in redundant number representation to reduce circuit dimensions while maintaining performance through efficient decision-making and path tracing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pipelining, look-ahead, and parallelism techniques are used to enhance computation speed and circuit performance, then circuit performance is improved, but circuit complexity and manufacturing cost increase
Solution Approach 1:
The ACS unit is divided into multiple independent ACS circuits that process different path metrics in parallel. Each ACS circuit handles specific computations independently, allowing the system to achieve high computation speed through parallel processing while keeping each individual circuit segment relatively simple and manageable.
Solution Approach 2:
The patent introduces a time dimension through pipelining by dividing the ACS operation into multiple stages that process data at different clock cycles. This allows overlapping of computation stages, enabling the circuit to process multiple path metrics simultaneously across different time cycles, thereby improving throughput without proportionally increasing the complexity of each stage.
2Productivity
If pipelining, look-ahead, and parallelism techniques are used to enhance computation speed and circuit performance, then circuit performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent uses identical copies of the ACS circuit structure to process multiple path metrics in parallel. By replicating the same proven circuit design multiple times, the system achieves high computation speed through parallelism while simplifying the manufacturing process, as the same standardized unit can be produced and integrated repeatedly without requiring complex custom designs for each component.
3Area of stationary object
If redundant number representation is used in path metrics, then circuit dimensions are reduced, but computation complexity increases
Solution Approach 1:
The patent changes the numerical representation parameter from standard binary to redundant number representation for path metrics. This parameter change allows the use of simpler addition circuits that do not require complex carry propagation logic, thereby reducing circuit dimensions. The redundant representation trades off some computational complexity in the addition operation for significant reductions in circuit area, particularly in the adder stages of the ACS unit.
Data Source
AI summary
An add-compare-select (ACS) unit generates first path metrics having a first bit-pair and a most significant bit-pair (MSB) each including a high bit and a low bit. A first ACS circuit produces the first bit-pair and a first carry. A limiting circuit generates the MSB based on the first carry, and limits the MSB to a first predetermined value. A MSB maximum select (MS) unit receives an MSB of second path metrics from another ACS unit, and compares the MSBs of the first and the second path metrics to determine MSB decision signals based on maximum likelihood selection. A MSB storage unit stores the MSB of the first path metrics. A reset unit resets the high bit of the MSB of the first path metrics to a second predetermined value when the high bits of the MSBs of the first and the second path metrics reach the first predetermined value.