Activated Memory Page Error Detection for Row Hammer Mitigation
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Solution Overview
Problem
Emerging memory technologies face challenges in detecting and mitigating errors due to a low hammer threshold and increased number of pages, leading to reduced reliability and security, particularly from row hammer effects.
Innovation Solution
Implementing a lightweight error detection scheme using even/odd parity check circuitry and error correction circuitry to identify errors in memory pages, followed by storing page addresses in a scrub queue for future correction using an ECC engine during memory management operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error detection methods are used in memory devices, then the device complexity is reduced, but the reliability is insufficient due to low hammer threshold and increased number of pages
Solution Approach 1:
The error detection mechanism is segmented into multiple independent components: parity check circuitry for basic error detection, scrub queue for tracking erroneous pages, and ECC engine for correction. This segmentation allows each component to perform its specific function efficiently without requiring the entire system to be overly complex.
Solution Approach 2:
The system performs preliminary actions by continuously monitoring memory pages using parity check circuitry and proactively adding erroneous pages to the scrub queue before errors propagate. This preliminary detection and tracking enables corrective actions to be taken in advance, improving reliability without requiring complex real-time correction mechanisms for every error.
2Reliability
If comprehensive error correction is implemented for all memory pages, then the reliability improves, but the productivity decreases due to increased scrubbing operations
Solution Approach 1:
Instead of applying comprehensive error correction uniformly to all memory pages, the system applies local quality by selectively targeting only those pages that have been identified as erroneous through parity checking and are queued for scrubbing. This localized approach ensures reliable correction where needed while avoiding unnecessary operations on healthy pages, thereby maintaining productivity.
Solution Approach 2:
The memory device performs self-service through autonomous error detection and correction operations. The parity check circuitry continuously monitors pages, the scrub queue automatically tracks erroneous pages, and the ECC engine performs correction without requiring external intervention. This self-service mechanism improves reliability while minimizing the impact on overall system productivity by operating in the background during memory management tasks.
3Reliability
If row hammer protection is enhanced with more sophisticated detection mechanisms, then the security improves, but the device complexity increases
Solution Approach 1:
The scrub queue acts as an intermediary mechanism between the parity check circuitry and the ECC engine. It mediates the error detection and correction process by storing and managing the list of erroneous pages, enabling the system to protect against row hammer effects through a manageable intermediate structure rather than requiring complex direct detection and correction pathways.
Data Source
AI summary
Systems, methods, and apparatus to detect errors in data being accessed in a memory array. In one approach, a memory device includes error detection circuitry, error correction circuitry, and a controller. The controller accesses portions of the memory array. The error detection circuitry determines whether an error exists in the accessed portions. Errors are detected by comparing parity stored in each portion with the computed parity for all data stored in that portion when being accessed. If an error is detected for a portion, an address of that portion is stored in a scrub queue for later correction using the error correction circuitry.