Activation Function Accelerator for Deep Learning Engine
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Solution Overview
Problem
Deep convolutional neural networks (DCNNs) face challenges in achieving flexibility, data locality, and fast execution due to the computational intensity of convolutional operations, particularly in tasks like image recognition, where traditional computing systems struggle with large image processing and complex pattern recognition.
Innovation Solution
An activation function accelerator is integrated into a deep learning engine, which includes a configurable accelerator framework and convolution accelerators, performing convolution operations with improved data locality and speed through dedicated hardware structures, such as the activation function accelerators that execute activation functions as piece-wise second-order polynomial approximations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional computing systems are used for DCNN operations, then general-purpose computing is maintained, but computational speed and energy efficiency deteriorate due to the computational intensity of convolutional operations
Solution Approach 1:
The patent replaces traditional general-purpose computing architectures with specialized hardware accelerators designed specifically for convolutional neural network operations. The DCNN processor includes dedicated convolution engines, activation function units, and dataflow architectures that substitute generic CPU/GPU mechanisms with purpose-built computational structures, achieving superior speed and energy efficiency for DCNN workloads
Solution Approach 2:
The DCNN processor is designed as a universal platform capable of executing various DCNN architectures and operations through configurable hardware components. The system can adapt to different network configurations, layer types, and computational patterns, providing multi-functional capability while maintaining optimized performance across diverse deep learning applications
2Speed
If data is stored in external memory for DCNN operations, then memory capacity is sufficient, but data access speed deteriorates due to memory access latency
Solution Approach 1:
The patent implements a hierarchical memory architecture where small, fast on-chip memory structures (registers, cache memory) are nested within the DCNN processor core, which itself is nested within the broader system memory hierarchy. This nested arrangement allows frequently accessed weights, activations, and intermediate results to be stored in proximity to computational units, dramatically reducing access latency while maintaining adequate total memory capacity through the layered structure
Solution Approach 2:
The patent transforms the traditional linear memory access model into a multi-dimensional dataflow architecture where data moves through specialized pipelines and buffers organized by spatial and temporal dimensions. This dimensional reorganization allows parallel data streams to be processed simultaneously through multiple access paths, effectively increasing data access speed without requiring proportional increases in total memory capacity
3Speed
If fixed-function hardware accelerators are used for DCNN operations, then computational speed is improved, but flexibility and adaptability deteriorate
Solution Approach 1:
The patent implements dynamically reconfigurable hardware components within the DCNN processor that can adapt their functionality based on the specific computational task. Configuration registers, programmable logic units, and configurable dataflow paths allow the hardware to be dynamically adjusted for different network architectures, layer types, and operational modes, maintaining high computational speed while providing flexibility across diverse deep learning applications
Solution Approach 2:
The patent utilizes programmable parameters and configuration settings that allow the hardware accelerator to change its operational characteristics based on the workload. By modifying parameters such as precision settings, dataflow patterns, activation function selections, and computational precision, the system maintains optimized performance speed while adapting to different DCNN models and requirements through parameter adjustment rather than physical reconfiguration
4Quantity of substance
If more memory is provided for DCNN operations, then data capacity is sufficient, but data locality deteriorates due to increased data movement
Solution Approach 1:
The patent segments the memory system into multiple specialized buffers and storage areas organized by data type and access pattern (weight buffers, activation buffers, intermediate result storage). This segmentation allows each memory segment to serve specific computational units with localized access, improving data locality by keeping relevant data close to where it is needed while collectively providing sufficient total data capacity across all segments
Data Source
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AI summary
Embodiments of a device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and an arithmetic unit (810) coupled to the reconfigurable stream switch. The arithmetic unit (810) has at least one input and at least one output. The at least one input is arranged to receive streaming data passed through the reconfigurable stream switch, and the at least one output is arranged to stream resultant data through the reconfigurable stream switch. The arithmetic unit (810) also has a plurality of data paths. At least one of the plurality of data paths is solely dedicated to performance of operations that accelerate an activation function represented in the form of a piece-wise second order polynomial approximation.