Active Area Patterning With Epitaxial Growth for Uniform Semiconductor Nodes

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Solution Overview

Problem

Conventional methods for fabricating semiconductor structures face challenges in achieving uniformity and cost-effectiveness, particularly in forming small and evenly sized active areas, which are crucial for meeting the requirements of advanced technology nodes.

Innovation Solution

A method involving a substrate with oxide, nitride, and silicon layers, where a patterned photoresist layer is formed, a mask layer and carbon layer are deposited and etched to expose the nitride layer, and an epitaxial layer is grown in opens to form active areas, with chemical mechanical planarization ensuring evenness and uniformity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional methods are used to fabricate semiconductor structures, then the manufacturing process is simpler, but the uniformity of active areas deteriorates

Engineering Contradiction:

Improveuniformity of active areasVSAvoidfabrication process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The fabrication process is divided into multiple distinct stages: forming patterned photoresist layer, depositing mask layer, coating carbon layer, selective etching, and epitaxial growth. Each stage serves a specific function in achieving uniform active areas, with the carbon layer providing precise etching control and the mask layer defining the pattern boundaries.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The carbon layer is deposited and patterned before the actual etching of the active areas. This preliminary patterning establishes precise etch boundaries and ensures uniform etching depth across all active areas, which is critical for achieving the required uniformity before the epitaxial growth step.

Inventive Principle:

Principle #10Preliminary action

2Length of moving object

If the critical dimension is continuously decreased, then the transistor size is reduced, but the uniformity of semiconductor elements deteriorates

Engineering Contradiction:

Improvetransistor sizeVSAvoiduniformity of semiconductor elements

Core Design Contradiction:

Length of moving objectVSManufacturing precision

Solution Approach 1:

The carbon layer is selectively deposited only in the regions where active areas will be formed, providing localized etching protection. This ensures that each active area receives precise etching control independent of its size, maintaining uniformity even as critical dimensions decrease to advanced technology nodes.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The method controls the etching process by adjusting the carbon layer thickness and composition, which directly affects the etching depth and uniformity. By optimizing these parameters, the process achieves consistent active area dimensions across varying transistor sizes and technology nodes.

Inventive Principle:

Principle #35Parameter changes

3Manufacturing precision

If better methods are used to fabricate semiconductor structures, then the uniformity improves, but the manufacturing complexity increases

Engineering Contradiction:

Improveuniformity of semiconductor elementsVSAvoidmanufacturing ease

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The carbon layer serves as an intermediary material that facilitates precise etching control. It acts as a sacrificial layer that defines the etching boundaries and protects surrounding areas, enabling uniform active area formation while using standard semiconductor fabrication equipment and processes.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enables the formation of small, evenly sized active areas, improving the yield rate and cost-effectiveness by ensuring precise and uniform semiconductor structure fabrication.

Implementation Method 1

growing an epitaxial layer from the top surface of the substrate in the plurality of opens to form the active areas

Methodology Applied

Scientific EffectEpitaxial growth: Epitaxy

Implementation Method 2

performing a photolithography to transfer the photoresist layer to be a plurality of photoresist objects on the silicon layer

Methodology Applied

Scientific EffectPhotolithography: Photography

Implementation Method 3

etching the carbon layer, the mask layer, and the silicon layer to expose a top surface of the nitride layer

Methodology Applied

Scientific EffectEtching: Ablation

Implementation Method 4

performing a chemical mechanical planarization to planarize the active areas and the oxide layer

Methodology Applied

Scientific EffectChemical mechanical planarization: Abrasion

Data Source

PatentUS20230386858A1Method of preparing active areas

Publication Date: 2023.11.30 NAN YA TECH

AI summary

The present disclosure provides a method of preparing active areas. The method includes the operations of: receiving a substrate having an oxide layer, a nitride layer, and a silicon layer thereon; forming a patterned photoresist layer on the silicon layer; depositing a mask layer to cover a contour of the patterned photoresist layer; coating a carbon layer on the mask layer; etching the carbon layer, the mask layer, and the silicon layer to expose a top surface of the nitride layer; forming a plurality of opens in the oxide layer to expose a top surface of the substrate; and growing an epitaxial layer from the top surface of the substrate in the plurality of opens to form the active areas.