Active-Area Gate Driver Circuit for Low-Power Display Devices
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Solution Overview
Problem
Existing display devices face challenges in minimizing bezel size and reducing power consumption, particularly in organic light emitting display devices.
Innovation Solution
The display device incorporates a gate driver disposed in the active area, omitting capacitors that cause significant power consumption, and utilizes a QB node connection to ensure reliability, thereby minimizing the non-active area and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitors are included in the gate driver circuit, then the gate signal stability is improved, but power consumption increases significantly
Solution Approach 1:
The patent removes the capacitor component from the gate driver circuit by utilizing the QB node's inherent charge storage capability. The QB node is connected to the gate electrode through a switching transistor, allowing the gate signal to be generated without requiring external capacitors, thus eliminating the associated power consumption while maintaining signal stability.
Solution Approach 2:
The QB node serves dual purposes: it functions as both a control node for the switching transistor and as a charge storage element equivalent to a capacitor. This self-service approach eliminates the need for separate capacitor components, reducing power consumption while maintaining the gate signal's stability through the QB node's voltage retention capability.
2Device complexity
If the gate driver is disposed in the non-active area, then the circuit layout is simplified, but the bezel size increases
Solution Approach 1:
The patent merges the gate driver circuit with the active display area by positioning the gate driver in the active area rather than separating it in the non-active area. This integration allows the gate driver to share the same physical space as the display pixels, eliminating the need for additional bezel space and reducing overall device footprint while maintaining circuit functionality.
Solution Approach 2:
The patent utilizes the vertical dimension within the active area to accommodate the gate driver circuit. By arranging the gate driver components (transistors, resistors, and QB nodes) in the same planar space as the display pixels, the design eliminates the horizontal bezel space that would otherwise be required, effectively transitioning from a two-dimensional separation to a space-efficient integrated layout.
3Use of energy by moving object
If capacitors are omitted from the gate driver, then power consumption is reduced, but circuit complexity changes
Solution Approach 1:
The patent extracts and removes the capacitor component from the traditional gate driver circuit configuration. By eliminating the capacitor and using the QB node's inherent charge storage capability instead, the circuit achieves lower power consumption while maintaining functional equivalence through a simplified transistor-based switching mechanism.
Solution Approach 2:
The patent changes the circuit configuration parameters by replacing the capacitor-based charge storage mechanism with a transistor-controlled QB node system. This parameter change involves modifying the circuit topology to use switching transistors that control the QB node's voltage, achieving the same functional outcome with reduced power consumption and different structural characteristics.
Data Source
AI summary
A display device includes a gate driver which supplies a gate signal to pixels and includes a plurality of stages, wherein each of the stages includes a pull-down unit which outputs a first voltage applied to a first voltage line responsive to a voltage of a Q node as the gate signal, a pull-up unit which outputs a second voltage applied to a second voltage line responsive to a voltage of a QB node as the gate signal, a Q node controller which controls the voltage of the Q node responsive to a start signal and a clock signal and a QB node controller which includes a first transistor including a gate electrode connected to a clock signal line to which the clock signal is supplied and controls the voltage of the QB node responsive to the clock signal, the start signal, and the voltage of the Q node.