Active Area Patterning with Variable-Sensitivity Resists
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the precise definition and patterning of small active areas, which becomes difficult with traditional electron beam lithography (EBL) as dimensions shrink, and extreme ultraviolet lithography (EUVL) is expensive and costly in terms of process and product costs.
Innovation Solution
The method involves using photosensitive materials with varying photosensitivities to define active areas arranged in different rows, allowing for the achievement of smaller dimensions (e.g., patterns with widths or lengths less than 37 nanometers) using electron beam lithography (EBL).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional electron beam lithography (EBL) is used to pattern smaller elements, then manufacturing cost is reduced, but manufacturing precision deteriorates as dimensions shrink below 37 nanometers
Solution Approach 1:
The patent segments the photosensitive material layer into multiple layers with different photosensitivities (first photosensitive material layer with higher sensitivity, second photosensitive material layer with lower sensitivity). This segmentation allows each layer to be exposed and developed independently at different stages, enabling precise patterning of sub-37nm features while maintaining cost-effectiveness by using modified EBL processes rather than expensive EUVL equipment.
Solution Approach 2:
The patent applies local quality by using photosensitive materials with different photosensitivities in different regions/layers. The first photosensitive material layer (higher sensitivity) is used for initial patterning, while the second photosensitive material layer (lower sensitivity) is used for subsequent finer patterning. This local differentiation of material properties enables progressive refinement of pattern dimensions with high precision at each stage.
2Manufacturing precision
If extreme ultraviolet lithography (EUVL) is used to achieve smaller dimensions, then manufacturing precision improves, but manufacturing cost increases significantly
Solution Approach 1:
Instead of using expensive EUVL for the entire patterning process, the patent segments the process into multiple EBL stages using photosensitive materials with different sensitivities. This segmentation allows high-precision sub-37nm patterning to be achieved through cumulative refinement across layers, avoiding the need for costly EUVL equipment while maintaining manufacturing precision.
Solution Approach 2:
The patent changes the parameter of photosensitivity by using materials with different sensitivity levels in different layers. By adjusting the photosensitivity parameter of the materials and controlling exposure doses progressively, the patent achieves high-precision patterning that would normally require EUVL, but using more cost-effective EBL equipment with modified multi-layer photoresist processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the precise formation of multiple active areas on a semiconductor substrate, achieving smaller dimensions while reducing the high costs associated with extreme ultraviolet lithography (EUVL).
Implementation Method 1
using photosensitive materials with varying photosensitivities to define active areas arranged in different rows, allowing for the achievement of smaller dimensions (e.g., patterns with widths or lengths less than 37 nanometers) using electron beam lithography (EBL)
Data Source
AI summary
The present application discloses a semiconductor structure includes a substrate having an active area, dielectric structures, and word lines. The active area is located between the dielectric structures. The word lines are situated in the active area and are surrounded by a first insulating film over the substrate. Each word line includes a word line channel film inwardly positioned in the first insulating film and the substrate, a word line electrode disposed over and surrounded by the word line channel film, and a word line insulating film conformally disposed between the word line channel film and the word line electrode. A lower portion of the word line channel film penetrates an upper portion of the substrate, while an upper portion of the word line channel film is positioned in the first insulating film above a top surface of the substrate.