Active Area Shapes Reducing SRAM Device Size
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Solution Overview
Problem
Conventional static random access memory (SRAM) architectures face challenges in scaling with gate all around (GAA) devices like nanosheet FET or vertical FET, due to difficulties in scaling the bitcell area due to contact and isolation requirements.
Innovation Solution
The development of transistor structures with optimized active area patterning techniques, where the active areas of complementary transistors are designed with specific shapes and doping impurities to enable better area scaling, utilizing a thin oxide layer for maskless reactive ion etching and self-aligned recess formation to reduce device size without violating groundrules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional SRAM architectures are used with GAA devices, then device functionality is maintained, but device size cannot be scaled down due to contact and isolation requirements
Solution Approach 1:
The patent transitions from planar 2D active areas to three-dimensional active areas that extend vertically along the sidewalls of the GAA channel. This dimensional change allows the active area to wrap around the channel structure, providing necessary contact and isolation functions while occupying less lateral space, thereby enabling continued device scaling
Solution Approach 2:
The active area is nested around the GAA channel structure, with the active area material conformally coating the channel sidewalls. This nested configuration integrates contact and isolation functions within the vertical profile of the device rather than requiring separate lateral structures, reducing the overall device footprint
2Volume of moving object
If active areas are patterned with conventional rectangular shapes, then manufacturing is simple, but device area scaling is limited
Solution Approach 1:
The patent employs curved and conformal active area patterns that follow the cylindrical or nanosheet geometry of the GAA channel, replacing conventional rectangular patterns. This curved configuration maximizes the active area utilization around the channel while minimizing the lateral footprint, enabling denser device packing
Solution Approach 2:
The active area is configured with different geometries at different locations: conformal sidewall coverage around the channel and specific planar extensions at contact regions. This localized geometric optimization provides enhanced scaling in regions where space is critical while maintaining necessary electrical connections
3Volume of moving object
If maskless reactive ion etching is used, then device size is reduced, but etch damage may increase
Solution Approach 1:
A thin oxide layer is deposited on the active area surface before the maskless reactive ion etching process. This preliminary oxide layer serves as a protective sacrificial layer that absorbs etch damage, preventing direct exposure of the underlying semiconductor structures to the harsh etch chemistry while still allowing the etch to proceed for size reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for continued scaling of SRAM devices by optimizing bottom source-drain active area design and non-rectangular patterning, enabling smaller SRAM bitcell sizes while maintaining necessary spacing and reducing etch damage, thus overcoming limitations in conventional SRAM scaling.
Implementation Method 1
utilizing a thin oxide layer for maskless reactive ion etching
Implementation Method 2
utilizing a thin oxide layer for maskless reactive ion etching and self-aligned recess formation
Data Source
AI summary
Methods form structures to include a first pair of complementary transistors (having first and second transistors) and a second pair of complementary transistors (having third and fourth transistors). An active area of the first transistor contacts an active area of the second transistor along a first common edge that is straight, and an active area of the third transistor contacts an active area of the fourth transistor along a second common edge that is straight and parallel to the first common edge. The active area of the second transistor has a third edge, opposite the first common edge, that has a non-linear shape, and the active area of the third transistor has a fourth edge, opposite the second common edge, that has the same non-linear shape. The non-linear shape of the third edge faces and is inverted relative to the non-linear shape of the fourth edge.