Non-Uniform Active Area Layout for STI Stress Reduction
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Solution Overview
Problem
Conventional uniform patterning of transistor active areas in semiconductor devices leads to higher stress in shallow trench isolation regions and processing difficulties, particularly as transistor sizes are scaled down, with FinFETs being more affected due to increased complexity in etching and chemical reactions.
Innovation Solution
The implementation of non-uniform active area patterns where edges conform to convex or concave arcs, reducing stress in shallow trench isolation regions and improving processing by adjusting the size of boundary active areas, allowing for larger contacts and reduced contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform active area patterning is used, then manufacturing simplicity is maintained, but stress in shallow trench isolation region increases and processing difficulty increases
Solution Approach 1:
The patent applies asymmetry by transitioning from uniform active area patterning to non-uniform patterning where active areas have varying lengths. Specifically, active areas adjacent to shallow trench isolation regions are made shorter than those in the center, creating an asymmetric length distribution that reduces stress concentration in the STI region while maintaining overall pattern simplicity through a systematic gradient approach.
Solution Approach 2:
The patent implements local quality by applying different active area lengths to different spatial locations. Active areas near the edges adjacent to STI regions are made shorter to locally reduce stress, while central active areas maintain longer lengths for optimal device performance. This localized differentiation addresses stress issues specifically where they occur without compromising overall device functionality.
2Manufacturing precision
If uniform active area patterning is used, then processing consistency is maintained, but etching difficulty increases due to loading effects
Solution Approach 1:
The patent applies parameter changes by systematically varying the length parameter of active areas across the substrate. Instead of maintaining a constant length, the active area length is adjusted as a function of position, creating a gradient where edge areas are shorter and central areas are longer. This parameter variation equalizes etching loading effects across different regions of the substrate, improving etching uniformity and processability.
3Reliability
If active area length is increased for higher performance, then device performance improves, but stress in active area and STI increases
Solution Approach 1:
The patent resolves this contradiction through asymmetric active area design where the length varies by location. Central active areas maintain longer lengths for optimal device performance and current drive, while edge active areas adjacent to STI regions are shortened to reduce stress concentration. This asymmetric approach allows the system to achieve high performance in critical regions without incurring excessive stress penalties.
Data Source
AI summary
In accordance with an embodiment, a semiconductor device comprises at least three active areas. The at least three active areas are proximate. Longitudinal axes of the at least three active areas are parallel, and each of the at least three active areas comprises an edge intersecting the longitudinal axis of the respective active area. The edges of the at least three active areas form an arc.