Active Array Substrate With High-K Gate Insulator
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Solution Overview
Problem
The existing gate oxide insulating layers in TFT-LCDs are too thin and cannot meet the increasing performance requirements due to the continuous reduction in device sizes, leading to issues with threshold voltage drift and circuit failure.
Innovation Solution
A method of manufacturing an active array substrate with a gate insulating layer comprising nanometer porous silicon and high dielectric constant particles, such as germanium, which increases the dielectric constant while maintaining a thin layer thickness, and a protection layer with a low dielectric constant to address signal crosstalk and RC circuit delay issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the gate oxide insulating layer is made thinner to reduce device size, then the device can be scaled down, but the dielectric constant decreases and threshold voltage drift occurs
Solution Approach 1:
The patent uses a composite gate insulating layer structure consisting of a first gate insulating layer (SiO2) and a second gate insulating layer (high-K dielectric material such as Ta2O5, HfO2, or Al2O3). This composite structure combines the advantages of both materials: SiO2 provides good interface characteristics and thermal stability, while the high-K dielectric material provides high dielectric constant to maintain sufficient gate control capability with thinner overall thickness, thereby preventing threshold voltage drift while enabling device scaling.
2Length of moving object
If the gate insulating layer thickness is reduced to meet scaling requirements, then device size decreases, but the storage charge capacity decreases
Solution Approach 1:
The patent changes the dielectric constant parameter by introducing high-K dielectric materials (Ta2O5 with K≈25, HfO2 with K≈20-25, or Al2O3 with K≈9) into the gate insulating layer. This parameter change allows the insulating layer to maintain thin thickness while achieving sufficient storage charge capacity through the high dielectric constant, effectively decoupling the relationship between thickness and charge capacity.
3Ease of manufacture
If conventional gate insulating materials are used, then the manufacturing process is simple, but the dielectric constant is insufficient for scaled-down devices
Solution Approach 1:
The patent modifies the dielectric constant parameter by selecting high-K dielectric materials (Ta2O5, HfO2, Al2O3) that can be deposited using conventional semiconductor manufacturing techniques such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). These materials achieve high dielectric constants (K>3.9 of SiO2) while being compatible with existing fabrication processes, thus improving reliability without significantly complicating manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the dielectric constant of the gate insulating layer, increases storage charge capacity, and improves device performance by reducing thickness and addressing signal crosstalk and RC circuit delay problems.
Implementation Method 1
the gate insulating layer comprises nanometer porous silicon and nanometer particles, and a dielectric constant of the nanometer particle is greater than a dielectric constant of the nanometer porous silicon
Implementation Method 2
The nanometer porous silicon can be made very thin, can reduce the thickness of the insulating dielectric layer
Implementation Method 3
The nanometer porous silicon itself is hydrophobic
Implementation Method 4
The nanometer porous silicon itself has many silicon pores, and the germanium nanometer particles can be deposited into the silicon pores without increasing the thickness of the nanometer porous silicon
Data Source
AI summary
A method of manufacturing an active array substrate, comprising: providing a substrate; forming gate electrodes on the substrate; forming a gate insulating layer, a semiconductor layer and an Ohmic contact layer on the transparent substrate and the gate electrodes in order; forming source electrodes and drain electrodes on the Ohmic contact layer; forming a protection layer on the source electrodes and the drain electrodes; and forming a pixel electrode layer on the protection layer, wherein the pixel electrode layer is electrically connected to the drain electrode. The gate insulating layer comprises nanometer porous silicon and nanometer particles, and a dielectric constant of the nanometer particle is greater than a dielectric constant of the nanometer porous silicon.