Active Bridge Back Powering Protection PoE Interface
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Solution Overview
Problem
Power over Ethernet (PoE) systems face inefficiencies due to high power dissipation in diode bridges and the risk of back powering in active FET bridges, which can damage components and violate standards.
Innovation Solution
An active bridge system using field-effect transistors (FETs) with current sensors and a powered device interface controller to detect current magnitude and polarity, transitioning FETs from closed to open configurations to prevent back powering when current is below a threshold, thereby reducing power loss and ensuring correct polarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If an active FET bridge is used to reduce power dissipation, then power efficiency is improved, but back powering risk increases which can damage components
Solution Approach 1:
The control circuit proactively monitors current direction and FET state before back powering can occur. When reverse current is detected or anticipated, the control circuit preemptively opens the FET switches to block potential back powering, preventing damage before it happens.
Solution Approach 2:
The system continuously monitors current flow through current sensors and feeds this information back to the control circuit. Based on the feedback signal indicating reverse current flow, the control circuit adjusts FET switching states in real-time to prevent back powering while maintaining efficient forward power transmission.
2Loss of energy
If FETs are kept in closed configuration for efficient power transmission, then power loss is reduced, but back powering cannot be prevented
Solution Approach 1:
The FET switching configuration is dynamically adjusted based on real-time current direction detection. The control circuit continuously changes FET states from closed (for efficient power transmission) to open (for back powering protection) as conditions require, optimizing both efficiency and protection.
Solution Approach 2:
The system changes the operational parameters of the FETs by switching between different resistance states (closed/open) based on current direction. This parameter change allows the system to transition between efficient power transmission mode and protection mode as needed.
3Measurement precision
If current monitoring threshold is set low for sensitive back powering detection, then protection accuracy is improved, but false triggering increases
Solution Approach 1:
The control circuit uses a threshold-based detection approach where it monitors current against a predetermined threshold level. This partial detection method provides sufficient sensitivity to detect back powering conditions while avoiding excessive sensitivity that would cause false triggering, achieving a practical balance between detection accuracy and system stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The active bridge system significantly reduces power loss and prevents back powering, enhancing efficiency and compliance with PoE standards by selectively controlling FET configurations based on current and voltage polarity.
Implementation Method 1
an active FET bridge configured to rectify input power supplied by power sourcing equipment to a power over Ethernet (PoE) powered device
Implementation Method 2
at least one current sensor configured to detect a magnitude of current
Data Source
AI summary
A method is disclosed to at least partially prevent back powering of power sourcing equipment. In one or more implementations, the method includes detecting a magnitude of current through a current sensor, such as a transistor and/or a resistor. The active FET bridge is configured to rectify input power supplied by power sourcing equipment to a power over Ethernet (PoE) powered device. The method also includes causing the transistor to transition from a closed configuration to an open configuration to at least substantially prevent current flow through the transistor when the magnitude of current is below a predefined threshold to at least substantially prevent back powering of the PSE.