Active Clamp Semiconductor Module for Erroneous Turn-On Suppression
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Solution Overview
Problem
Existing semiconductor modules face issues with erroneous turn-on due to sharp changes in drain-source voltage, leading to inefficient operation and potential damage, as they lack effective mechanisms to prevent activation during deactivation states.
Innovation Solution
The semiconductor module integrates a first chip with a main transistor and a second chip containing an active clamp circuit, including a clamp transistor, capacitor, and pull-down resistor, which are electrically connected to inhibit erroneous turn-on by limiting gate-source voltage increases during sharp voltage changes, thereby reducing parasitic impedance and inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a discrete semiconductor device with a main transistor is used, then the device structure is simple, but erroneous turn-on occurs due to sharp changes in drain-source voltage
Solution Approach 1:
The semiconductor device is divided into two separate chips: a first chip containing the main transistor and a second chip containing the active clamp circuit (clamp transistor, capacitor, and pull-down resistor). This segmentation allows the active clamp circuit to be integrated without increasing the complexity of the main transistor structure, while effectively preventing erroneous turn-on through the clamp circuit's voltage limiting action.
Solution Approach 2:
The active clamp circuit acts as an intermediary protective mechanism between the main transistor and the harmful voltage spikes. The clamp transistor and capacitor work together to limit gate-source voltage increases during sharp drain-source voltage changes, preventing erroneous turn-on without requiring modifications to the main transistor itself.
2Reliability
If an active clamp circuit is integrated to prevent erroneous turn-on, then operational reliability is improved, but the number of components increases
Solution Approach 1:
The clamp transistor, capacitor, and pull-down resistor are merged into a single integrated active clamp circuit on the second chip. This consolidation provides complete erroneous turn-on protection functionality while minimizing the number of separate components, as all essential elements are combined in one integrated unit.
Solution Approach 2:
The active clamp circuit is designed to act preemptively by detecting sharp changes in drain-source voltage and immediately limiting gate-source voltage increases before erroneous turn-on can occur. The pull-down resistor pre-configures the gate voltage to a safe state, and the capacitor rapidly responds to voltage spikes, preventing the harmful effect before it manifests.
3Speed
If the conductive path is shortened to reduce parasitic impedance, then the response speed to voltage changes improves, but the layout complexity increases
Solution Approach 1:
The active clamp circuit is implemented on a separate second chip rather than integrating all components on the same chip as the main transistor. This dimensional separation (using multiple chips stacked or positioned closely) allows for optimized conductive paths with minimal parasitic impedance while avoiding layout complexity constraints of a single-chip design. The short conductive path is achieved through vertical or close-proximity inter-chip connections.
Data Source
AI summary
A semiconductor module comprises: a first chip that includes a main transistor including an electron transit layer which serves as a main drift layer; a second chip that includes at least a part of an active clamp circuit including a clamp transistor which operates on the basis of an increase in the drain-source voltage of the main transistor; a connection member that electrically connects the main transistor and the active clamp circuit; and a sealing resin that seals the first chip, the second chip, and the connection member. The clamp transistor includes a sub-drift layer composed of a material different from that of the main drift layer.