Active Clock Shielding Using Power Gating Lines Against Coupling Noise

Solution Overview

Problem

As semiconductor integration increases, signal interference (coupling noise) between signal lines becomes more problematic, leading to the need for additional shielding lines that can degrade integration and increase design overhead.

Innovation Solution

Implementing an active clock shielding structure using power gating signal transmission lines or retention signal transmission lines as shielding line pairs with clock signal transmission lines, eliminating the need for additional shielding lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If additional shielding lines are included to prevent signal interference, then signal interference is reduced, but the degree of integration is degraded and design overhead increases

Engineering Contradiction:

Improvesignal interferenceVSAvoiddegree of integration

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The power gating signal transmission line is designed to serve dual functions: transmitting the power gating signal to the power gating circuit and simultaneously functioning as a shielding line for the clock signal transmission line. This multi-functionality eliminates the need for separate shielding lines, maintaining high degree of integration while preventing signal interference through the shielding effect of the adjacent power gating signal line.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Object-affected harmful factors

If additional shielding lines are included to prevent signal interference, then signal interference is reduced, but design overhead increases

Engineering Contradiction:

Improvesignal interferenceVSAvoiddesign overhead

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The power gating signal transmission line is designed to serve dual functions: transmitting the power gating signal to the power gating circuit and simultaneously functioning as a shielding line for the clock signal transmission line. This multi-functionality eliminates the need for separate shielding lines, maintaining high degree of integration while preventing signal interference through the shielding effect of the adjacent power gating signal line.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Object-affected harmful factors

If the clock signal transmission line is shielded by dedicated shielding lines, then coupling noise is reduced, but the area occupied by signal lines increases

Engineering Contradiction:

Improvecoupling noiseVSAvoidarea occupied by signal lines

Core Design Contradiction:

Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The shielding function is merged with the power gating signal transmission line rather than being implemented as a separate dedicated shielding structure. The power gating signal line is positioned adjacent to the clock signal transmission line and utilizes its electromagnetic field to provide shielding, thereby reducing coupling noise without requiring additional space for separate shielding lines.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The power gating signal transmission line is designed to serve dual functions: transmitting the power gating signal to the power gating circuit and simultaneously functioning as a shielding line for the clock signal transmission line. This multi-functionality eliminates the need for separate shielding lines, maintaining high degree of integration while preventing signal interference through the shielding effect of the adjacent power gating signal line.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8013628B2Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same

Publication Date: 2011.09.06 SAMSUNG ELECTRONICS CO LTD

AI summary

A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.