Active CMOS Rectifier for Wireless Power
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Solution Overview
Problem
Conventional rectifying circuits, such as those using Schottky diodes and CMOS transistors, are not suitable for high-power wireless charging of portable consumer electronics due to inefficiencies and incompatibility with CMOS technologies.
Innovation Solution
A rectifying circuit incorporating NMOS transistors, an impedance matching network, an RF block circuit, and a gate driver circuit, which includes capacitive and inductive elements to efficiently convert RF signals to DC voltage, with adaptive biasing to handle higher power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Schottky diode rectifiers are used for high-frequency operation, then rectification efficiency is improved, but compatibility with CMOS technologies deteriorates
Solution Approach 1:
The patent replicates the functional behavior of Schottky diode rectifiers using CMOS transistor circuits that mimic the same rectification characteristics, allowing high-frequency operation while maintaining CMOS compatibility through circuit-level imitation rather than using actual Schottky diodes
Solution Approach 2:
The patent replaces the physical Schottky diode component with an equivalent CMOS transistor-based circuit implementation, substituting a semiconductor device with a transistor circuit that achieves the same electrical function through different physical mechanisms
2Adaptability or versatility
If conventional CMOS recovery circuits are used for low-power applications, then CMOS compatibility is improved, but power handling capability deteriorates
Solution Approach 1:
The patent implements adaptive biasing circuits that dynamically adjust the operating point of CMOS transistors based on the input power level, allowing the circuit to maintain optimal efficiency across a wide range of power conditions from low-power RFID to high-power wireless charging applications
Solution Approach 2:
The patent changes key operating parameters such as gate bias voltages and transistor sizing to optimize performance for different power levels, enabling the same CMOS circuit architecture to handle both low-power and high-power applications by adjusting circuit parameters rather than redesigning the entire system
3Volume of moving object
If higher frequency of operation is used to reduce circuit size, then miniaturization is improved, but suitability of conventional diode rectifiers deteriorates
Solution Approach 1:
The patent creates CMOS transistor circuits that copy the rectification function of diodes, enabling operation at higher frequencies where conventional diodes become unsuitable, while maintaining compact circuit dimensions through integrated transistor implementation
Solution Approach 2:
The patent designs a universal CMOS rectifier circuit that can operate across multiple frequency ranges and power levels, replacing the need for frequency-specific diode designs with a single adaptable transistor-based circuit architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed rectifying circuit efficiently converts RF signals to DC voltage, capable of handling higher power requirements, making it suitable for charging portable consumer electronics while being compatible with CMOS technologies.
Implementation Method 1
an impedance matching network, disposed between the antenna and the drain terminals of the first and second NMOS transistors
Implementation Method 2
which includes capacitive and inductive elements to efficiently convert RF signals to DC voltage
Implementation Method 3
which includes capacitive and inductive elements to efficiently convert RF signals to DC voltage
Data Source
AI summary
A rectifying circuit includes, in part, first and second NMOS transistors, an impedance matching network, and an RF block circuit. The source and gate terminals of the first NMOS transistor respectively receive the ground potential and a biasing voltage. The second NMOS transistor has a gate terminal coupled to the drain terminal of the first NMOS transistor, a drain terminal coupled to the gate terminal of the first NMOS transistor, and a source terminal receiving the ground potential. The impedance matching network is disposed between the antenna and the drain terminals of the first and second NMOS transistors. The RF block circuit is coupled between the drain terminals of the first and second NMOS transistors and the output terminal of the rectifying circuit. The RF block circuit is adapted to prevent the RF signal from flowing into the output terminal of the rectifying circuit.