Active Contact Structure for Capacitance-Stable Semiconductor Scaling
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Solution Overview
Problem
As semiconductor devices scale down, there is a need for improved capacitance and electrical stability between contacts, which existing multi-gate transistors with three-dimensional channels struggle to achieve effectively.
Innovation Solution
The semiconductor device design includes an active pattern on a substrate with gate structures, source/drain patterns, and specific contact configurations, such as lower and upper active contacts, and an etching stop film, to enhance capacitance control and stability, with the etching stop film extending along the upper surface of the lower active contact without reaching the upper surface of the gate capping pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors with three-dimensional channels are used for scaling, then integration density and current control capability are improved, but capacitance control and electrical stability between contacts deteriorate
Solution Approach 1:
The contact structure is divided into multiple segments: lower active contact, upper active contact, and etching stop film layers. This segmentation allows independent optimization of each contact layer's properties and positioning, enabling better control of capacitance and electrical stability while maintaining high integration density through the multi-gate transistor architecture
Solution Approach 2:
The etching stop film serves as an intermediary layer between the lower active contact and upper active contact. This intermediate layer provides precise spacing control and electrical isolation, mediating the interaction between contacts to reduce parasitic capacitance while maintaining structural integrity and electrical stability
2Productivity
If pitch between semiconductor devices is decreased to increase integration density, then productivity is improved, but capacitance control and electrical stability between contacts worsen
Solution Approach 1:
The contact structure extends in the vertical dimension with multiple stacked layers (lower active contact, etching stop film, upper active contact) rather than relying solely on horizontal spacing. This vertical dimensionality provides additional degrees of freedom for controlling capacitance and electrical stability, allowing pitch reduction while maintaining performance through precise vertical positioning and layer thickness control
Data Source
AI summary
A semiconductor device includes; an active pattern on a substrate, gate structures in which each gate structure includes a gate electrode intersecting the active pattern and a gate capping pattern on the gate electrode, a source/drain pattern disposed on the active pattern between adjacent gate structures, a lower active contact connected to the source/drain pattern, an etching stop film extending along an upper surface of the lower active contact without contacting an upper surface of the gate capping pattern, and an upper active contact connected to the lower active contact, wherein a bottom surface of the upper active contact is lower than the upper surface of the gate capping pattern.