Active Contact Segments and Offset Vias for Semiconductor Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration and reliability due to limitations in device design and manufacturing processes, particularly in avoiding electrical shorts and optimizing the placement of vias in relation to active contacts.
Innovation Solution
The semiconductor device design includes a substrate with active patterns, gate electrodes, source/drain patterns, and active contacts with specific segment structures and via placements that prevent electrical shorts, allowing for reduced device size and increased integration by offsetting the second via from the second segment of the active contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the second via is placed directly on the second segment of the active contact, then electrical connection is achieved, but electrical shorts may occur between the via and the active contact
Solution Approach 1:
An insulating pattern is introduced as an intermediary element between the second via and the second segment of the active contact. This insulating pattern fills the space between them, preventing direct electrical contact while allowing the via to maintain its electrical connection function, thus eliminating the harmful electrical short effect
Solution Approach 2:
The contact hole is divided into multiple segments: a first portion containing the first segment of the active contact, and a second portion containing the second segment. The insulating pattern is placed in the second portion, creating spatial segmentation that separates the conductive elements and prevents electrical shorts
2Productivity
If the device size is reduced for high integration, then integration density increases, but the distance between PMOSFET and NMOSFET regions must be minimized which increases risk of electrical shorts
Solution Approach 1:
The insulating pattern extends vertically within the contact hole structure, utilizing the vertical dimension to provide electrical isolation. This allows horizontal spacing between PMOSFET and NMOSFET regions to be minimized for high integration while maintaining reliable electrical isolation through the vertical presence of the insulating pattern
Solution Approach 2:
The insulating pattern serves as a mediator that enables reduced spacing between complementary transistor regions while preventing electrical shorts. It allows the device to achieve high integration density without compromising electrical isolation between PMOSFET and NMOSFET regions
Data Source
AI summary
A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.