Active Contact Structure for Low-Capacitance Semiconductor Scaling
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Solution Overview
Problem
As semiconductor devices scale down, there is a need for improved capacitance and electrical stability between contacts, which existing multi-gate transistors with 3D channels struggle to achieve effectively.
Innovation Solution
The semiconductor device design includes an active pattern on a substrate with gate structures, source/drain patterns, and specific contact configurations such as lower and upper active contacts, an interlayer insulating film, and an etching stop film, where the upper surface of the etching stop film does not extend to the interlayer or gate capping patterns, allowing for improved contact formation and reduced capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch of semiconductor devices is decreased to increase integration density, then productivity is improved, but electrical stability between contacts deteriorates and capacitance increases
Solution Approach 1:
The patent introduces a vertical dimension to contact separation by forming the bottom surface of the upper active contact at a lower level than the upper surface of the gate capping pattern. This vertical offset creates additional spacing between contacts in the depth direction, reducing capacitance and improving electrical stability while allowing pitch to be decreased for higher integration density.
2Reliability
If the bottom surface of the upper active contact is positioned lower than the upper surface of the gate capping pattern, then capacitance between contacts is reduced and electrical stability is improved, but device complexity increases
Solution Approach 1:
The contact structure is segmented into distinct vertical levels: the lower active contact at one level and the upper active contact with its bottom surface positioned lower than the gate capping pattern upper surface. This segmentation creates natural electrical isolation and reduces capacitance while maintaining a systematic, manufacturable structure through defined vertical positioning.
Data Source
AI summary
A semiconductor device includes; an active pattern on a substrate, gate structures in which each gate structure includes a gate electrode intersecting the active pattern and a gate capping pattern on the gate electrode, a source/drain pattern disposed on the active pattern between adjacent gate structures, a lower active contact connected to the source/drain pattern, an etching stop film extending along an upper surface of the lower active contact without contacting an upper surface of the gate capping pattern, and an upper active contact connected to the lower active contact, wherein a bottom surface of the upper active contact is lower than the upper surface of the gate capping pattern.