Active-Degeneration DAC Circuit for PLL Flicker Noise Reduction
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Solution Overview
Problem
Digital-to-analog converters (DACs) in phase-locked loops (PLLs) operating at millimeter-wave frequencies face challenges in meeting stringent integrated phase noise specifications and wide frequency tuning ranges, particularly due to high flicker noise from PMOS transistors, which is difficult to filter and increases area and power consumption.
Innovation Solution
The implementation of a DAC circuit with active degeneration using non-DAC transistor devices as variable resistances at the input side of DAC transistor devices, controlled by a feedback signal from an operating condition circuit, to reduce low-frequency 1/f noise and adjust bias, thereby improving noise performance without increasing the size and power consumption of the DAC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the DAC size is increased to reduce flicker noise, then noise performance is improved, but area and power consumption increase
Solution Approach 1:
The patent introduces non-DAC transistor devices as intermediary variable resistance elements coupled to the input side of DAC transistor devices. These intermediary devices provide active degeneration that reduces flicker noise without requiring an increase in the size of the main DAC structure, thereby resolving the contradiction between noise performance and area consumption.
Solution Approach 2:
The patent changes the resistance parameter dynamically by using non-DAC transistor devices configured as variable resistances. The control circuit adjusts the bias of these variable resistance devices to optimize the trade-off between flicker noise reduction and power consumption, allowing the system to adapt resistance values without permanently increasing DAC area.
2Object-affected harmful factors
If the DAC size is increased to reduce flicker noise, then noise performance is improved, but power consumption increases
Solution Approach 1:
The non-DAC transistor devices serve as intermediary elements that reduce flicker noise through active degeneration without requiring the main DAC to operate at higher power levels. This intermediary approach allows noise reduction while maintaining power-efficient operation of the core DAC structure.
Solution Approach 2:
The control circuit dynamically adjusts the bias parameter of the non-DAC transistor devices to optimize the balance between flicker noise reduction and power consumption. By varying the resistance and bias current of the variable resistance devices, the system achieves noise performance improvements without proportionally increasing overall power consumption.
3Object-affected harmful factors
If variable resistance devices are added to reduce flicker noise, then noise performance is improved, but device complexity increases
Solution Approach 1:
The non-DAC transistor devices serve multiple functions: they act as variable resistances for flicker noise reduction, are controlled by a dedicated control circuit that adjusts their bias, and integrate with the existing DAC structure without requiring completely separate noise reduction circuitry. This multi-functionality approach reduces the relative complexity increase compared to dedicated single-purpose noise reduction circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces flicker noise in the DAC, enhancing the PLL's noise performance and supporting wide frequency tuning ranges while maintaining a compact and power-efficient design.
Implementation Method 1
The implementation of a DAC circuit with active degeneration using non-DAC transistor devices as variable resistances at the input side of DAC transistor devices, controlled by a feedback signal from an operating condition circuit, to reduce low-frequency 1/f noise
Data Source
AI summary
A digital to analog converter (DAC) includes a plurality of DAC transistor devices having an input side configured to be selectively coupled to a system voltage based on a digital input signal and an output side configured to provide an analog output signal, a plurality of non-DAC transistor devices coupled to the input side of the DAC transistor devices, the non-DAC transistor devices configured as variable resistances, and a control circuit configured to adjust a bias of the non-DAC transistor devices.