Active Delay Line Topology for Wide Bandwidth in Small IC Area
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Solution Overview
Problem
Existing broad-band delay lines for integrated circuits face challenges in achieving high bandwidth while being power-efficient, as they either require large circuit areas or consume high power to increase circuit speed.
Innovation Solution
A broadband active delay cell is designed using a cascade topology with each delay cell comprising a first and second summing amplifier, incorporating a negative feedback loop and a feedforward path, which allows for high bandwidth by performing weighted sums and utilizing a differential circuit topology with NMOS transistors and current sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transmission lines or distributed L-C networks are used to achieve broad-band delay, then bandwidth is improved, but circuit area increases significantly
Solution Approach 1:
The patent replaces passive transmission lines and distributed L-C networks with an active delay cell using transistors (M1-M4) and resistors (R1-R4) to achieve delay functionality. This substitution of mechanical/passive structures with active electronic components reduces circuit area while maintaining broad-band performance through the active circuit topology.
Solution Approach 2:
The patent changes the operating parameters of the active delay cell by using equalizing components (Ce1, Ce2, Re1, Re2) that are tuned to match the pole-zero frequencies of the circuit. This parameter matching technique extends the bandwidth of the active delay cell while keeping the circuit area compact, resolving the contradiction between bandwidth and area.
2Speed
If power is increased to drive up circuit speed in active delay lines, then bandwidth is improved, but power consumption increases
Solution Approach 1:
The patent introduces equalizing feedback paths with components (Ce1, Ce2, Re1, Re2) that provide frequency-dependent feedback to compensate for the rolling off of gain at higher frequencies. This feedback mechanism extends the bandwidth of the active delay cell without requiring increased power consumption, as it uses the existing signal energy rather than additional power to achieve broadband performance.
Solution Approach 2:
The patent employs dynamic equalization where the feedback network adapts the frequency response of the delay cell in real-time across the bandwidth. The equalizing components create frequency-dependent gain compensation that dynamically maintains flat response across broad bandwidth without requiring static high-power operation, thus achieving bandwidth extension power-efficiently.
3Area of stationary object
If conventional delay cells are used, then circuit area is reduced, but bandwidth is highly limited
Solution Approach 1:
The patent uses equalizing feedback paths with components (Ce1, Ce2, Re1, Re2) that provide frequency-dependent compensation to extend the bandwidth of the compact active delay cell. This feedback mechanism allows the small-area circuit to achieve broad-band performance by dynamically adjusting the frequency response rather than relying on large passive structures.
Solution Approach 2:
The patent changes the frequency response parameters of the delay cell through equalization, matching the pole-zero frequencies to create a flat response across broad bandwidth. This parameter optimization allows the compact active circuit to achieve broadband performance that would otherwise require large transmission lines or distributed networks.
Data Source
AI summary
A broad-band active delay line includes a plurality of broad-band active delay cells configured in a cascade topology. Each broad-band active delay cell includes a feedback loop and a feedforward path to achieve a high bandwidth.