Active Device Array Substrate with Localized Gate-to-Drain Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing active device array substrates for LCD panels suffer from non-uniform display luminance due to different feed-through effects generated by scan signal transmission lines, leading to issues like V-shaped dark or bright bands, which deteriorate the display quality.
Innovation Solution
The design incorporates active devices with varying gate-to-drain capacitances based on the location of pixel units, compensating for the differences in feed-through effects by adjusting the overlap areas of gates and drains, ensuring consistent electrical performance and display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan signal transmission lines are used to connect scan lines, then signal transmission is enabled, but different feed-through effects are generated on pixel units adjacent to nodes versus those not adjacent to nodes, causing non-uniform display luminance
Solution Approach 1:
The patent applies local quality by differentiating the gate-to-drain capacitance values based on the location of pixel units. Pixel units adjacent to nodes are assigned a first gate-to-drain capacitance value, while pixel units not adjacent to nodes are assigned a second gate-to-drain capacitance value. This localized differentiation compensates for the varying feed-through effects experienced by different pixel units, thereby achieving uniform display luminance across the entire display region.
2Ease of manufacture
If uniform gate-to-drain capacitance is used for all pixel units, then manufacturing is simplified, but display quality deteriorates due to non-uniform electrical performance caused by feed-through effects
Solution Approach 1:
The patent implements local quality by assigning different gate-to-drain capacitance values to pixel units based on their location relative to nodes. This approach maintains manufacturing feasibility while achieving precise electrical performance consistency across different pixel units, effectively resolving the contradiction between ease of manufacture and manufacturing precision.
3Reliability
If pixel units adjacent to nodes have different electrical characteristics, then feed-through effects are compensated, but device complexity increases due to multiple capacitance values
Solution Approach 1:
The patent manages device complexity by implementing a straightforward location-based classification system. Pixel units are simply categorized as either adjacent to nodes or not adjacent to nodes, with each category assigned a corresponding capacitance value. This approach achieves reliable display quality compensation without introducing excessive complexity into the device configuration.
Solution Approach 2:
The patent applies parameter changes by adjusting the gate-to-drain capacitance values based on the spatial location of pixel units. By changing the capacitance parameter according to location, the patent compensates for feed-through effects and achieves consistent display quality across different regions of the display.
Data Source
AI summary
An active device array substrate includes a substrate, scan lines disposed on the substrate, data lines intersected with the scan lines, scan signal transmission lines, and pixel units. The scan signal transmission lines are intersected with the scan lines. Each scan signal transmission line connects one scan line through a node. The pixel unit electrically connects the corresponding data line and the corresponding scan line and includes an active device and a pixel electrode. The active device has a gate, a source, and a drain. The pixel electrode electrically connects the drain. In the pixel units not adjacent to the nodes, a gate-to-drain capacitance of each active device is Cgd1. In the pixel units adjacent to the nodes, the gate-to-drain capacitances of some active devices are Cgd2, the gate-to-drain capacitances of the other active devices are Cgd1, and Cgd1≠Cgd2.