Active Device Array Substrate Fabrication with Integrated Photo Sensors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for fabricating active device array substrates with integrated photo sensors face challenges due to poor quantum efficiency and signal distortion caused by insufficient poly-silicon thickness and light interference, requiring additional photolithography and etching processes, which increase costs and reduce competitiveness.
Innovation Solution
A method for fabricating active device array substrates that integrates photo sensors without additional photolithography and etching processes by forming the active layer and bottom electrode simultaneously with the second patterned conductive layer, using a process compatible with the existing substrate fabrication, thereby reducing costs and enhancing sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional photolithography and etching processes are used to form the photosensitive material pattern, then the photosensitive material can be properly patterned, but the manufacturing cost increases and process complexity increases
Solution Approach 1:
The patent merges the patterning of the photosensitive material with the existing patterning process of the light-shielding electrode layer. Both layers are patterned simultaneously using the same photolithography and etching processes, eliminating the need for separate additional patterning steps. This is achieved by designing the patterns such that the photosensitive material and light-shielding electrode layer can be formed in the same process sequence, thereby reducing process complexity while maintaining patterning precision.
2Manufacturing precision
If additional photolithography and etching processes are used to form the photosensitive material pattern, then the photosensitive material can be properly patterned, but the manufacturing cost increases
Solution Approach 1:
The patent combines the formation of the photosensitive material pattern with the existing light-shielding electrode layer patterning process. By using the same photolithography and etching steps for both layers, the manufacturing cost is reduced as no additional process equipment, materials, or labor are required beyond what is already allocated for the electrode layer patterning.
3Reliability
If the photosensitive material size is made smaller than the light-shielding electrode layer, then the photosensitive characteristics are improved, but additional patterning processes are required
Solution Approach 1:
The patent achieves the size differential between the photosensitive material and light-shielding electrode layer through integrated patterning design. The patterns are configured such that the photosensitive material region is naturally smaller than the electrode layer region, and both are formed in the same patterning sequence. This eliminates the need for additional patterning processes while maintaining the optimized size relationship for improved photosensitive characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces process complexity and costs while improving the sensitivity of the photo sensor by eliminating the need for extra photolithography and etching steps, allowing for more accurate patterning and better light shielding, thus enhancing the overall performance of the active device array substrate.
Implementation Method 1
the photo sensor can be used as an input device of an optical touch panel. When the user touch the optical touch panel with his/her fingers or other articles, the photo sensor integrated in the LCD detects the change in light and output a corresponding signal
Data Source
AI summary
A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.