Active Fan-Out Circuit for Parallel Test Signal Isolation
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Solution Overview
Problem
Current test systems face limitations in parallelism, signal performance, and test time overhead due to issues with mechanical relays, passive switches, and wire-OR configurations, particularly at high frequencies and in multi-device testing environments.
Innovation Solution
An active fan-out system with integrated circuits that electrically isolate multiple input/output terminals, allowing parallel output and input operations while maintaining signal integrity and reducing test time overhead, enabling independent parametric measurements and high-frequency testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If mechanical relays are used for address fan-out, then device isolation is achieved, but system reliability deteriorates due to bulkiness and failure proneness
Solution Approach 1:
The patent replaces mechanical relays with solid-state switches (MOSFETs) to eliminate mechanical wear and failure issues. The solid-state switches provide the same electrical isolation function without the bulkiness and reliability problems of mechanical components, directly resolving the contradiction between reliability and complexity.
Solution Approach 2:
The patent changes the operating parameters of the switches by using MOSFETs with specific gate voltages (e.g., 5V for switching, 10V for keeping open) to achieve reliable operation. This parameter optimization ensures the switches maintain high isolation performance while being more reliable than mechanical relays.
2Reliability
If solid state switches are used for address fan-out, then reliability improves, but signal performance deteriorates due to ON resistance and capacitance
Solution Approach 1:
The patent introduces buffer stages between the solid-state switches and the test equipment to compensate for the ON resistance and capacitance of the switches. These buffers act as intermediaries that restore signal integrity, allowing the use of reliable solid-state switches without sacrificing signal performance.
Solution Approach 2:
The patent optimizes the switch operating parameters by using MOSFETs with specific gate voltages (5V for switching, 10V for keeping open) and appropriate pull-up/pull-down resistor values (e.g., 1kΩ) to minimize ON resistance and capacitance effects, thereby maintaining signal performance while ensuring reliability.
3Productivity
If address lines are split into multiple lines for fan-out, then parallelism increases, but signal integrity deteriorates due to intrinsic impedance mismatches and reflections
Solution Approach 1:
The patent introduces buffer stages at the fan-out points to act as impedance matching intermediaries. These buffers compensate for the intrinsic impedance mismatches created by splitting address lines, preventing signal reflections and maintaining integrity while enabling increased parallelism.
Solution Approach 2:
The patent optimizes the impedance parameters of the test equipment and wiring to match the split line configurations. By adjusting these parameters, the system maintains signal integrity even with multiple parallel lines, resolving the contradiction between parallelism and signal integrity.
4Productivity
If multiple devices are connected to fan-out lines, then parallelism increases, but test time overhead increases due to sequential operation requirements
Solution Approach 1:
The patent makes the test system dynamic by allowing independent control of each device through the solid-state switches. This enables the system to switch between devices rapidly and perform parallel testing operations, reducing test time overhead while maintaining high parallelism.
Solution Approach 2:
The patent ensures continuous useful action by maintaining the test signal flow through buffer stages and solid-state switches without interruption. This allows multiple devices to be tested in parallel continuously, eliminating idle time and reducing overall test time overhead.
Data Source
AI summary
In accordance with one embodiment of the invention, a system is provided that comprises a first terminal for receiving an input testing signal during operation; a plurality of input/output terminals coupled with the first terminal; wherein the input/output terminals are configured to parallel output respective output testing signals during parallel output operation; wherein the input/output terminals are configured to parallel input testing response signals during parallel input operation from devices under test; and wherein each of the input/output terminals is electrically isolated during operation from the remaining plurality of input/output terminals.