Active FET ESD Triggering With Voltage Surge Immunity
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Solution Overview
Problem
Microelectronic devices face damage from overvoltage transients, with existing protective circuits either providing inadequate protection against both electrostatic discharge (ESD) and voltage surge events or being susceptible to damage during sustained voltage surges due to high clamping voltages or fast protection mechanisms.
Innovation Solution
A microelectronic device incorporating a field effect transistor (FET) with an ESD trigger circuit and gate control circuit, along with a transient detection circuit, which differentiates between ESD and voltage surge events by providing an on-state signal for ESD and an off-state signal for voltage surges, ensuring the FET remains off during voltage surges to prevent damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If protective circuits are designed with high clamping voltages to protect against both ESD and voltage surge events, then protection coverage is improved, but protection effectiveness against voltage-sensitive circuits deteriorates
Solution Approach 1:
The protective circuit is segmented into two distinct circuits: a first protective circuit designed specifically for ESD events with optimized clamping characteristics, and a second protective circuit designed for voltage surge events with different clamping characteristics. This segmentation allows each circuit to be optimized for its specific protection target, resolving the contradiction between broad protection coverage and effective protection for voltage-sensitive circuits.
2Speed
If protective circuits are designed for fast protection against ESD events, then ESD protection speed is improved, but susceptibility to damage during sustained voltage surge events worsens
Solution Approach 1:
The protection system is divided into two specialized circuits: the first protective circuit responds quickly to ESD events with fast clamping action, while the second protective circuit is designed to handle sustained voltage surge events with appropriate clamping characteristics. This segmentation resolves the contradiction by assigning different speed and durability requirements to separate circuits rather than requiring a single circuit to satisfy both conflicting requirements.
Solution Approach 2:
The protective circuits exhibit dynamic behavior where the first protective circuit activates quickly for fast ESD transients, while the second protective circuit becomes more prominent during sustained surge conditions. The system dynamically adapts its protection characteristics based on the nature of the transient event, allowing fast response when needed while maintaining surge immunity.
3Device complexity
If a single protective circuit is used for both ESD and voltage surge events, then device complexity is reduced, but protection precision for different transient types deteriorates
Solution Approach 1:
Rather than using a single general-purpose protective circuit, the system segments protection into two specialized circuits with different clamping voltage characteristics optimized for their respective transient types. This segmentation improves detection precision and protection effectiveness for different transient events, accepting increased circuit complexity as necessary for differentiated protection.
Data Source
AI summary
A microelectronic device has a protected line and a reference line, and an active field effect transistor (FET) coupled between the protected line and the reference line. The microelectronic device includes an electrostatic discharge (ESD) trigger circuit coupled to the gate of the active FET, to turn on the active FET when an ESD event occurs on the protected line. The microelectronic device further includes a transient detection circuit having a high bandwidth detector, an ESD detector, and an output driver. The ESD detector is configured to provide a CLEAR signal to the output driver when an ESD event occurs on the protected line. The output driver is configured to turn off the active FET when a voltage surge, which can damage the active FET, occurs on the protected line, but enable operation of the active FET by the ESD trigger circuit during an ESD event.