Contact-Over-Active-Gate Structure for Dense 10 nm FinFET Layouts

The pitch quartering process segments the patterning into multiple distinct stages: forming mandrels at a first pitch, depositing spacers, selectively removing mandrels, and forming features at a quartered pitch. This segmentation allows each stage to be optimized independently, achieving the required manufacturing precision at 10nm node by breaking down the complex patterning challenge into manageable steps with controlled variability at each stage.

The methodology employs preliminary actions by first forming mandrels and spacers before final feature definition. The spacers are formed as preliminary structures that guide subsequent etching and material deposition. This preliminary action sequence establishes a framework that ensures precise feature placement and reduces variability in the final pattern, addressing the reliability concerns at advanced nodes.

The merged fin pitch quartering technique applies local quality by creating different fin pitch configurations in different regions of the semiconductor device. Some regions have merged fins with tighter spacing while others maintain standard spacing. This allows optimization of transistor density in specific high-performance areas while maintaining manufacturability and performance control in other regions, thus increasing overall density without sacrificing device performance optimization capability.

The methodology changes geometric parameters by transitioning from uniform fin pitch to variable fin pitch configurations. The merged fin approach creates regions with different pitch values (quartered pitch vs. original pitch), enabling density optimization in critical areas while maintaining parameter control through the structured, repeatable nature of the pitch quartering process. This parameter variation achieves higher transistor density while preserving manufacturing precision through controlled implementation.

The pitch quartering process employs a nested doll structure where spacers are formed around mandrels, then mandrels are removed and new spacers are formed around the first spacers. Each patterning cycle nests within the previous structure, systematically quartering the pitch. This nested approach achieves high transistor density through a structured sequence of operations that, while complex, follows a predictable and repeatable pattern that can be integrated into existing fabrication workflows.

The methodology adds dimensional complexity by utilizing vertical spacer deposition and lateral pattern transfer. Instead of attempting to create quartered pitch in a single planar step, the process uses the vertical dimension for spacer formation and then transfers the pattern laterally. This dimensional approach manages fabrication complexity by distributing operations across different spatial dimensions rather than concentrating all complexity in a single patterning plane.

The multi-layer trench isolation structure is formed as a preliminary measure before fin patterning and transistor fabrication. By establishing the isolation trenches and filling them with appropriate dielectric materials in advance, the process creates a controlled environment that enables precise fin stress management during subsequent steps. This preliminary action ensures that fin stress can be optimized without requiring additional steps later, maintaining productivity while achieving precise stress control.

The fin trim isolation technique applies local quality by selectively removing or modifying isolation material in specific regions adjacent to fins. This localized modification allows precise control of fin stress in critical areas where performance is most sensitive, while leaving other regions unchanged. This targeted approach achieves superior fin stress control with minimal impact on overall fabrication throughput, as only specific local areas require the additional trim steps.